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author | Gabor Juhos <juhosg@openwrt.org> | 2012-04-21 12:30:47 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-04-21 12:30:47 +0000 |
commit | 16459281356e9f8f7ec5d6b7bb7ef3ade8910483 (patch) | |
tree | f8387d4e4de98b8a2a3dbe05ce6e45d95df6a8b3 /target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | |
parent | fb69e28eaf2499fad9c67aa0f41ebf587dc5d602 (diff) | |
download | upstream-16459281356e9f8f7ec5d6b7bb7ef3ade8910483.tar.gz upstream-16459281356e9f8f7ec5d6b7bb7ef3ade8910483.tar.bz2 upstream-16459281356e9f8f7ec5d6b7bb7ef3ade8910483.zip |
ramips: rt305x: fix CPU clock detection on RT3352
SVN-Revision: 31401
Diffstat (limited to 'target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c')
-rw-r--r-- | target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c | 43 |
1 files changed, 31 insertions, 12 deletions
diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c index 522bb44639..4a99cf39e2 100644 --- a/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c +++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c @@ -33,20 +33,39 @@ void __init rt305x_clocks_init(void) u32 t; t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG); - t = ((t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK); - - switch (t) { - case RT305X_SYSCFG_CPUCLK_LOW: - rt305x_cpu_clk.rate = 320000000; - break; - case RT305X_SYSCFG_CPUCLK_HIGH: - rt305x_cpu_clk.rate = 384000000; - break; + + if (soc_is_rt305x() || soc_is_rt3350()) { + t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & + RT305X_SYSCFG_CPUCLK_MASK; + switch (t) { + case RT305X_SYSCFG_CPUCLK_LOW: + rt305x_cpu_clk.rate = 320000000; + break; + case RT305X_SYSCFG_CPUCLK_HIGH: + rt305x_cpu_clk.rate = 384000000; + break; + } + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + rt305x_uart_clk.rate = rt305x_sys_clk.rate; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else if (soc_is_rt3352()) { + t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & + RT3352_SYSCFG0_CPUCLK_MASK; + switch (t) { + case RT3352_SYSCFG0_CPUCLK_LOW: + rt305x_cpu_clk.rate = 384000000; + break; + case RT3352_SYSCFG0_CPUCLK_HIGH: + rt305x_cpu_clk.rate = 400000000; + break; + } + rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; + rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10; + rt305x_wdt_clk.rate = rt305x_sys_clk.rate; + } else { + BUG(); } - rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3; - rt305x_uart_clk.rate = rt305x_sys_clk.rate; - rt305x_wdt_clk.rate = rt305x_sys_clk.rate; } /* |