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author | Gabor Juhos <juhosg@openwrt.org> | 2012-02-13 15:17:59 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-02-13 15:17:59 +0000 |
commit | e532fa5fd42501e468051addfac454ab70128b04 (patch) | |
tree | 4ee21b4ab08ac16ca698ea7b263143a3ad4a4f46 /target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h | |
parent | 3bfbc69bc20091d4b9ae0cd065388b1fdab4978f (diff) | |
download | upstream-e532fa5fd42501e468051addfac454ab70128b04.tar.gz upstream-e532fa5fd42501e468051addfac454ab70128b04.tar.bz2 upstream-e532fa5fd42501e468051addfac454ab70128b04.zip |
ramips: add preliminary support for the RT3662/RT3883 SoCs
SVN-Revision: 30495
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h')
-rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h new file mode 100644 index 0000000000..7ff0b358e2 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h @@ -0,0 +1,55 @@ +/* + * Ralink RT3662/RT3883 specific CPU feature overrides + * + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 + +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 1 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_RALINK_CPU_FEATURE_OVERRIDES_H */ |