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author | Gabor Juhos <juhosg@openwrt.org> | 2009-09-04 15:08:26 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2009-09-04 15:08:26 +0000 |
commit | 8d8a4e727481a58495f8c3b9dfd2e92650d85e10 (patch) | |
tree | 08dcd82358322b24a2b85a010a18144d7721ac83 /target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h | |
parent | 8691bbb699556ab797d74d635cc360732d9b92de (diff) | |
download | upstream-8d8a4e727481a58495f8c3b9dfd2e92650d85e10.tar.gz upstream-8d8a4e727481a58495f8c3b9dfd2e92650d85e10.tar.bz2 upstream-8d8a4e727481a58495f8c3b9dfd2e92650d85e10.zip |
add GPIO configuration feature
SVN-Revision: 17512
Diffstat (limited to 'target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h')
-rw-r--r-- | target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h index 98308ffe01..d29880611e 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt288x_regs.h @@ -46,6 +46,7 @@ #define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */ #define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/ #define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/ +#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */ #define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */ #define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */ @@ -75,6 +76,15 @@ #define RT2880_RESET_FE BIT(18) #define RT2880_RESET_PCM BIT(19) +#define RT2880_GPIO_MODE_I2C BIT(0) +#define RT2880_GPIO_MODE_UART0 BIT(1) +#define RT2880_GPIO_MODE_SPI BIT(2) +#define RT2880_GPIO_MODE_UART1 BIT(3) +#define RT2880_GPIO_MODE_JTAG BIT(4) +#define RT2880_GPIO_MODE_MDIO BIT(5) +#define RT2880_GPIO_MODE_SDRAM BIT(6) +#define RT2880_GPIO_MODE_PCI BIT(7) + #define RT2880_INTC_INT_TIMER0 BIT(0) #define RT2880_INTC_INT_TIMER1 BIT(1) #define RT2880_INTC_INT_UART0 BIT(2) |