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authorAdrian Schmutzler <freifunk@adrianschmutzler.de>2019-07-03 23:22:36 +0200
committerDaniel Golle <daniel@makrotopia.org>2019-07-10 17:36:29 +0200
commit3b0264eddbc94f43a015a965b9eb3e12cfce0655 (patch)
treedc30fa67ba4983dbb763ab9ce37689f64c637f59 /target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts
parent6a104ac77206158c593cc7572c46eca6d3f4717f (diff)
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ramips/rt305x: Name DTS files based on scheme
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Diffstat (limited to 'target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts')
-rw-r--r--target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts99
1 files changed, 99 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts b/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts
new file mode 100644
index 0000000000..702d779aa2
--- /dev/null
+++ b/target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+#include "rt3050.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ compatible = "jcg,jhr-n805r", "ralink,rt3050-soc";
+ model = "JCG JHR-N805R";
+
+ aliases {
+ led-boot = &led_system;
+ led-failsafe = &led_system;
+ led-running = &led_system;
+ led-upgrade = &led_system;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system: system {
+ label = "jhr-n805r:blue:system";
+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&pinctrl {
+ state_default: pinctrl0 {
+ gpio {
+ ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf";
+ ralink,function = "gpio";
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ partition@50000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x50000 0x3b0000>;
+ };
+ };
+ };
+};
+
+&ethernet {
+ mtd-mac-address = <&factory 0x2e>;
+};
+
+&esw {
+ mediatek,portmap = <0x3e>;
+};
+
+&wmac {
+ ralink,mtd-eeprom = <&factory 0>;
+};