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| author | Michael Pratt <mcpratt@pm.me> | 2021-04-03 14:42:51 -0400 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2021-06-23 14:22:18 +0800 |
| commit | 0976b6c4262a11a8d0dab9aeb64f5cdee266c44a (patch) | |
| tree | 87b1b5830ce2614e04e34d5301bf462e123e416e /target/linux/ramips/dts/mt7620a_sercomm_na930.dts | |
| parent | de5394a29dae9356a830d043e76591698411e97a (diff) | |
| download | upstream-0976b6c4262a11a8d0dab9aeb64f5cdee266c44a.tar.gz upstream-0976b6c4262a11a8d0dab9aeb64f5cdee266c44a.tar.bz2 upstream-0976b6c4262a11a8d0dab9aeb64f5cdee266c44a.zip | |
ramips: mt7620: use DTS to set PHY base address for external PHYs
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Diffstat (limited to 'target/linux/ramips/dts/mt7620a_sercomm_na930.dts')
| -rw-r--r-- | target/linux/ramips/dts/mt7620a_sercomm_na930.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7620a_sercomm_na930.dts b/target/linux/ramips/dts/mt7620a_sercomm_na930.dts index 329ecc5ea8..1ffc0a2bc8 100644 --- a/target/linux/ramips/dts/mt7620a_sercomm_na930.dts +++ b/target/linux/ramips/dts/mt7620a_sercomm_na930.dts @@ -167,6 +167,7 @@ &gsw { mediatek,port4-gmac; + mediatek,ephy-base = /bits/ 8 <8>; }; &ehci { |