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authorYuheiOKAWA <tochiro.srchack@gmail.com>2016-10-10 10:24:42 +0900
committerJohn Crispin <john@phrozen.org>2016-10-15 11:36:51 +0200
commit4050cfebdaa001d498c396f24dd67771541b710e (patch)
treee7f4f574a91e63f5f4079aecbf0781fb20eb0839 /target/linux/ramips/dts/VR500.dts
parent8a2a20e71e2909f84dab47e51dfda9e292a6c1ae (diff)
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ramips: add support for Planex VR500.
SOC: MT7621A RAM: 256MiB NOR: MX25L51245G Non Wireless Router. Issue: soft reboot problem. SPI Flash do not exit 4byte address mode. Signed-off-by: Yuhei Okawa <tochiro.srchack@gmail.com>
Diffstat (limited to 'target/linux/ramips/dts/VR500.dts')
-rw-r--r--target/linux/ramips/dts/VR500.dts92
1 files changed, 92 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/VR500.dts b/target/linux/ramips/dts/VR500.dts
new file mode 100644
index 0000000000..3cddce6fbe
--- /dev/null
+++ b/target/linux/ramips/dts/VR500.dts
@@ -0,0 +1,92 @@
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+/ {
+ compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
+ model = "Planex VR500";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "vr500:green:power";
+ gpios = <&gpio1 13 1>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 15 1>;
+ linux,code = <0x198>;
+ };
+ };
+};
+
+&xhci {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ linux,modalias = "m25p80";
+ spi-max-frequency = <10000000>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "firmware";
+ reg = <0x50000 0x3fb0000>;
+ };
+ };
+};
+
+&pinctrl {
+ state_default: pinctrl0 {
+ gpio {
+ ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci";
+ ralink,function = "gpio";
+ };
+ };
+};
+
+&pcie {
+ status = "disabled";
+};