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authorRobert Marko <robimarko@gmail.com>2023-06-11 19:32:52 +0200
committerChristian Marangi <ansuelsmth@gmail.com>2023-06-16 11:11:08 +0200
commitf02f6aaa8d4e1025ab4aa9f569123e57f689f4e5 (patch)
treea5cd6920cb495282ceaa8ddbbb4adf9297b8e2b4 /target/linux/qualcommax/files
parentde9955a62f6aab6eafb2cfdffc4829ee97e69c04 (diff)
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ipq807x: rename target to qualcommax
Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
Diffstat (limited to 'target/linux/qualcommax/files')
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts322
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts73
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi311
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts46
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts389
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts410
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts522
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts243
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts308
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts191
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts487
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi19
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi123
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi228
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi531
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi188
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts445
-rw-r--r--target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts376
18 files changed, 5212 insertions, 0 deletions
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts
new file mode 100644
index 00000000000..2c9cbd5b3cd
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8070-cax1800.dts
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
+
+/dts-v1/;
+
+#include "ipq8074-512m.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Edimax CAX1800";
+ compatible = "edimax,cax1800", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_system_red;
+ led-failsafe = &led_system_red;
+ led-running = &led_system_green;
+ led-upgrade = &led_system_red;
+ /* Aliases as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp5;
+ label-mac-device = &dp5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_1";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_red: system-red {
+ label = "red:system";
+ gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_green: system-green {
+ label = "green:system";
+ gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "rootfs";
+ reg = <0x0000000 0x3400000>;
+ };
+ };
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-select = <0>;
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ use-default-sizes;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsblenv";
+ reg = <0x480000 0x10000>;
+ };
+
+ partition@490000 {
+ label = "0:appsbl";
+ reg = <0x490000 0xa0000>;
+ read-only;
+ };
+
+ partition@530000 {
+ label = "0:appsbl_1";
+ reg = <0x530000 0xa0000>;
+ read-only;
+ };
+
+ partition@5d0000 {
+ label = "0:art";
+ reg = <0x5d0000 0x40000>;
+ read-only;
+ };
+
+ partition@610000 {
+ label = "0:ethphyfw";
+ reg = <0x610000 0x80000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x1e>; /* lan port bitmap */
+ switch_wan_bmp = <0x20>; /* wan port bitmap */
+ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@4 {
+ port_id = <5>;
+ phy_address = <4>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8075>;
+ label = "lan";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Edimax-CAX1800";
+ qcom,ath11k-fw-memory-mode = <1>;
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts
new file mode 100644
index 00000000000..f3e82e22511
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8071-ax3600.dtsi"
+
+/ {
+ model = "Xiaomi AX3600";
+ compatible = "xiaomi,ax3600", "qcom,ipq8074";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_yellow: system-yellow {
+ label = "yellow:system";
+ gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+ };
+
+ network-yellow {
+ label = "yellow:network";
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ network-blue {
+ label = "blue:network";
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ aiot {
+ label = "blue:aiot";
+ gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tpt";
+ };
+ };
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi0: wifi@1,0 {
+ status = "okay";
+
+ compatible = "qcom,ath10k";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
+ nvmem-cell-names = "calibration";
+ nvmem-cells = <&caldata_qca9889>;
+ };
+ };
+};
+
+&wifi {
+ qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
new file mode 100644
index 00000000000..c18cef52f39
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+#include "ipq8074-512m.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_system_yellow;
+ led-failsafe = &led_system_yellow;
+ led-running = &led_system_blue;
+ led-upgrade = &led_system_yellow;
+ label-mac-device = &dp2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:qsee";
+ reg = <0x200000 0x300000>;
+ read-only;
+ };
+
+ partition@500000 {
+ label = "0:devcfg";
+ reg = <0x500000 0x80000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "0:rpm";
+ reg = <0x580000 0x80000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:cdt";
+ reg = <0x600000 0x80000>;
+ read-only;
+ };
+
+ partition@680000 {
+ label = "0:appsblenv";
+ reg = <0x680000 0x80000>;
+ };
+
+ partition@700000 {
+ label = "0:appsbl";
+ reg = <0x700000 0x100000>;
+ read-only;
+ };
+
+ partition@800000 {
+ label = "0:art";
+ reg = <0x800000 0x80000>;
+ read-only;
+
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_dp2: macaddr@6 {
+ reg = <0x6 0x6>;
+ };
+
+ macaddr_dp3: macaddr@c {
+ reg = <0xc 0x6>;
+ };
+
+ macaddr_dp4: macaddr@12 {
+ reg = <0x12 0x6>;
+ };
+
+ macaddr_dp5: macaddr@18 {
+ reg = <0x18 0x6>;
+ };
+
+ caldata_qca9889: caldata@4d000 {
+ reg = <0x33000 0x844>;
+ };
+ };
+
+ partition@880000 {
+ label = "bdata";
+ reg = <0x880000 0x80000>;
+ };
+
+ partition@900000 {
+ /* This is crash + crash_syslog parts combined */
+ label = "pstore";
+ reg = <0x900000 0x100000>;
+ };
+
+ /* Make the first rootfs a dedicated ubi partition for kernel */
+ partition@a00000 {
+ label = "ubi_kernel";
+ reg = <0xa00000 0x23c0000>;
+ };
+
+ /* Place the real rootfs in the original second rootfs and
+ * expand it to the end of the nand
+ */
+ rootfs: partition@2dc0000 {
+ label = "rootfs";
+ reg = <0x2dc0000 0xd240000>;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8075_4: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x1e>; /* lan port bitmap */
+ switch_wan_bmp = <0x20>; /* wan port bitmap */
+ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@4 {
+ port_id = <5>;
+ phy_address = <4>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "wan";
+ nvmem-cells = <&macaddr_dp2>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_dp3>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_dp4>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_dp5>;
+ nvmem-cell-names = "mac-address";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-fw-memory-mode = <1>;
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts
new file mode 100644
index 00000000000..6611a8fe27a
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8071-ax3600.dtsi"
+
+/ {
+ model = "Redmi AX6";
+ compatible = "redmi,ax6", "qcom,ipq8074";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_system_yellow: system-yellow {
+ label = "yellow:system";
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ network-blue {
+ label = "blue:network";
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ network-yellow {
+ label = "yellow:network";
+ gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+/* AX6 can both have NAND of 256MiB or 128MiB.
+ * To be on the safe side, assume 128MiB of NAND.
+ */
+&rootfs {
+ reg = <0x2dc0000 0x5220000>;
+};
+
+&wifi {
+ qcom,ath11k-calibration-variant = "Redmi-AX6";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts
new file mode 100644
index 00000000000..357b6368d9d
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8071-eap102.dts
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2022, Matthew Hagan <mnhagan88@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-ac-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Edgecore EAP102";
+ compatible = "edgecore,eap102", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
+ led-boot = &led_system_green;
+ led-failsafe = &led_system_green;
+ led-running = &led_system_green;
+ led-upgrade = &led_system_green;
+ /* Aliases as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp5;
+ ethernet1 = &dp6;
+ label-mac-device = &dp5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_1";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_wanpoe {
+ label = "green:wanpoe";
+ gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_wlan2g {
+ label = "green:wlan2g";
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1radio";
+ };
+
+ led_wlan5g {
+ label = "green:wlan5g";
+ gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0radio";
+ };
+
+ led_system_green: led_system {
+ label = "green:power";
+ gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ button_pins: button_pins {
+ reset_button {
+ pins = "gpio66";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_spi1 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsblenv";
+ reg = <0x480000 0x10000>;
+ };
+
+ partition@490000 {
+ label = "0:appsbl";
+ reg = <0x490000 0xc0000>;
+ read-only;
+ };
+
+ partition@550000 {
+ label = "0:appsbl_1";
+ reg = <0x530000 0xc0000>;
+ read-only;
+ };
+
+ partition@610000 {
+ label = "0:art";
+ reg = <0x610000 0x40000>;
+ read-only;
+ };
+
+ partition@650000 {
+ label = "0:ethphyfw";
+ reg = <0x650000 0x80000>;
+ read-only;
+ };
+
+ partition@6d0000 {
+ label = "0:product_info";
+ reg = <0x6d0000 0x80000>;
+ read-only;
+ };
+
+ partition@750000 {
+ label = "priv_data1";
+ reg = <0x750000 0x10000>;
+ read-only;
+ };
+
+ partition@760000 {
+ label = "priv_data2";
+ reg = <0x760000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "rootfs1";
+ reg = <0x0000000 0x3400000>;
+ };
+
+ partition@3400000 {
+ label = "0:wififw";
+ reg = <0x3400000 0x800000>;
+ read-only;
+ };
+
+ partition@3c00000 {
+ label = "rootfs2";
+ reg = <0x3c00000 0x3400000>;
+ };
+
+ partition@7000000 {
+ label = "0:wififw_1";
+ reg = <0x7000000 0x800000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ qca8081_24: ethernet-phy@24 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <24>;
+ reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+ };
+
+ qca8081_28: ethernet-phy@28 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x3e>; /* lan port bitmap */
+ switch_wan_bmp = <0x40>; /* wan port bitmap */
+ switch_mac_mode = <0xff>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@4 {
+ port_id = <5>;
+ phy_address = <24>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ port@5 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8081_28>;
+ label = "wan";
+};
+
+&dp6 {
+ status = "okay";
+ phy-handle = <&qca8081_24>;
+ label = "lan";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Edgecore-EAP102";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
new file mode 100644
index 00000000000..5521a480b8a
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "QNAP 301w";
+ compatible = "qnap,301w", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ /*
+ * Aliases as required by u-boot
+ * to patch MAC addresses
+ */
+ led-boot = &led_system_red;
+ led-failsafe = &led_system_red;
+ led-running = &led_pwr_green;
+ led-upgrade = &led_system_red;
+ ethernet0 = &dp1;
+ ethernet1 = &dp2;
+ ethernet2 = &dp3;
+ ethernet3 = &dp4;
+ ethernet4 = &dp5;
+ ethernet5 = &dp6_syn;
+ label-mac-device = &dp1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ wps-button {
+ label = "wps";
+ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset-button {
+ label = "reset";
+ gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&leds_pins>;
+ pinctrl-names = "default";
+
+ led_system_green: led-system-green {
+ label = "green:system";
+ gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led_system_red: led-system-red {
+ label = "red:system";
+ gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led_pwr_green: led-pwr-green {
+ label = "green:pwr";
+ gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-wifi-green {
+ label = "green:wifi";
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-lan4-green {
+ label = "green:lan4";
+ gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-lan4-amber {
+ label = "amber:lan4";
+ gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led-lan3-green {
+ label = "green:lan3";
+ gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-lan3-amber {
+ label = "amber:lan3";
+ gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led-lan2-green {
+ label = "green:lan2";
+ gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-lan2-amber {
+ label = "amber:lan2";
+ gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led-lan1-green {
+ label = "green:lan1";
+ gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-lan1-amber {
+ label = "amber:lan1";
+ gpios = <&tlmm 15 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led-10g-1-green {
+ label = "green:10g_1";
+ gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-10g-1-amber {
+ label = "amber:10g_1";
+ gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led-10g-2-green {
+ label = "green:10g_2";
+ gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led-10g-2-amber {
+ label = "amber:10g_2";
+ gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+ };
+};
+
+&tlmm {
+
+ mdio_pins: mdio-state {
+ mdc-pins {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ button_pins: button-state {
+ wps-pins {
+ pins = "gpio57";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ rst-pins {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ leds_pins: leds-state {
+ pins = "gpio1", "gpio3", "gpio4", "gpio6", "gpio7", "gpio8",
+ "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio42",
+ "gpio51", "gpio52", "gpio54", "gpio56";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "qcom,smem-part";
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ aqr113c_0: ethernet-phy@0 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ };
+
+ aqr113c_8: ethernet-phy@8 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+
+ qca8075_16: ethernet-phy@16 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <16>;
+ };
+
+ qca8075_17: ethernet-phy@17 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <17>;
+ };
+
+ qca8075_18: ethernet-phy@18 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <18>;
+ };
+
+ qca8075_19: ethernet-phy@19 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <19>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ /* According to the stock dts from the QNAP gpl drop
+ * the emmc has a problem with the hs400 > hs200 speed switch.
+ * Therefore remove the mmc-hs400-1_8v property
+ */
+ /delete-property/ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ vqmmc-supply = <&l11>;
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x3e>; /* lan port bitmap */
+ switch_wan_bmp = <0xc0>; /* wan port bitmap */
+ switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <16>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <17>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <18>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <19>;
+ };
+ port@4 {
+ port_id = <5>;
+ phy_address = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ port@5 {
+ port_id = <6>;
+ phy_address = <0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_16>;
+ label = "lan4";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_17>;
+ label = "lan3";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_18>;
+ label = "lan2";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_19>;
+ label = "lan1";
+};
+
+&dp5 {
+ status = "okay";
+ qcom,mactype = <1>;
+ phy-handle = <&aqr113c_8>;
+ label = "10g-1";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&aqr113c_0>;
+ label = "10g-2";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "QNAP-301w";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts
new file mode 100644
index 00000000000..801aa056045
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-ax9000.dts
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Xiaomi AX9000";
+ compatible = "xiaomi,ax9000", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_system_yellow;
+ led-failsafe = &led_system_yellow;
+ led-running = &led_system_blue;
+ led-upgrade = &led_system_yellow;
+ label-mac-device = &dp5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps"; /* Labeled Mesh on the device */
+ gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led_system_yellow: system-yellow {
+ label = "yellow:system";
+ gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ };
+
+ network-yellow {
+ label = "yellow:network";
+ gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ };
+
+ network-blue {
+ label = "blue:network";
+ gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ top-red {
+ label = "red:top";
+ gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "keep";
+ };
+
+ top-green {
+ label = "green:top";
+ gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "keep";
+ };
+
+ top-blue {
+ label = "blue:top";
+ gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "keep";
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "gpio0", "gpio2";
+ function = "blsp5_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:bootconfig";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "0:bootconfig1";
+ reg = <0x280000 0x80000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "0:qsee";
+ reg = <0x300000 0x300000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:qsee_1";
+ reg = <0x600000 0x300000>;
+ read-only;
+ };
+
+ partition@900000 {
+ label = "0:devcfg";
+ reg = <0x900000 0x80000>;
+ read-only;
+ };
+
+ partition@980000 {
+ label = "0:devcfg_1";
+ reg = <0x980000 0x80000>;
+ read-only;
+ };
+
+ partition@a00000 {
+ label = "0:apdp";
+ reg = <0xa00000 0x80000>;
+ read-only;
+ };
+
+ partition@a80000 {
+ label = "0:apdp_1";
+ reg = <0xa80000 0x80000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ label = "0:rpm";
+ reg = <0xb00000 0x80000>;
+ read-only;
+ };
+
+ partition@b80000 {
+ label = "0:rpm_1";
+ reg = <0xb80000 0x80000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "0:cdt";
+ reg = <0xc00000 0x80000>;
+ read-only;
+ };
+
+ partition@c80000 {
+ label = "0:cdt_1";
+ reg = <0xc80000 0x80000>;
+ read-only;
+ };
+
+ partition@d00000 {
+ label = "0:appsblenv";
+ reg = <0xd00000 0x80000>;
+ };
+
+ partition@d80000 {
+ label = "0:appsbl";
+ reg = <0xd80000 0x100000>;
+ read-only;
+ };
+
+ partition@e80000 {
+ label = "0:appsbl_1";
+ reg = <0xe80000 0x100000>;
+ read-only;
+ };
+
+ partition@f80000 {
+ label = "0:art";
+ reg = <0xf80000 0x80000>;
+ read-only;
+
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_dp1: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+
+ macaddr_dp2: macaddr@6 {
+ reg = <0x6 0x6>;
+ };
+
+ macaddr_dp3: macaddr@c {
+ reg = <0xc 0x6>;
+ };
+
+ macaddr_dp4: macaddr@12 {
+ reg = <0x12 0x6>;
+ };
+
+ macaddr_dp5: macaddr@18 {
+ reg = <0x18 0x6>;
+ };
+
+ caldata_qca9889: caldata@4d000 {
+ reg = <0x4d000 0x844>;
+ };
+ };
+
+ partition@1000000 {
+ label = "bdata";
+ reg = <0x1000000 0x80000>;
+ };
+
+ partition@1080000 {
+ /* This is crash + crash_syslog parts combined */
+ label = "pstore";
+ reg = <0x1080000 0x100000>;
+ };
+
+ partition@1180000 {
+ label = "ubi_kernel";
+ reg = <0x1180000 0x3800000>;
+ };
+
+ partition@4980000 {
+ label = "rootfs";
+ reg = <0x4980000 0xb680000>;
+ };
+ };
+ };
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8081: ethernet-phy@24 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <24>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x1e>; /* lan port bitmap */
+ switch_wan_bmp = <0x20>; /* wan port bitmap */
+ switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xc>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@4 {
+ port_id = <5>;
+ phy_address = <24>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_0>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_dp1>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_dp2>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_dp3>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_dp4>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8081>;
+ label = "wan";
+ nvmem-cells = <&macaddr_dp5>;
+ nvmem-cell-names = "mac-address";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
+ };
+ };
+};
+
+&pcie_qmp1 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+
+ bridge@1,0 {
+ reg = <0x00010000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ compatible = "qcom,ath10k";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath10k-calibration-variant = "Xiaomi-AX9000";
+ nvmem-cell-names = "calibration";
+ nvmem-cells = <&caldata_qca9889>;
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Xiaomi-AX9000";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts
new file mode 100644
index 00000000000..5468e9e1fb8
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-dl-wrx36.dts
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2022, Robert Marko <robimarko@gmail.com> */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Dynalink DL-WRX36";
+ compatible = "dynalink,dl-wrx36", "qcom,ipq8074";
+
+ aliases {
+ led-boot = &led_system_red;
+ led-failsafe = &led_system_red;
+ led-running = &led_system_blue;
+ led-upgrade = &led_system_red;
+ serial0 = &blsp1_uart5;
+ /* Aliases as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp6_syn;
+ ethernet1 = &dp4;
+ ethernet2 = &dp3;
+ ethernet3 = &dp2;
+ ethernet4 = &dp1;
+ label-mac-device = &dp6_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_1";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led_system_red: system-red {
+ label = "red:system";
+ gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "qcom,smem-part";
+ };
+ };
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8081: ethernet-phy@28 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x3e>; /* lan port bitmap */
+ switch_wan_bmp = <0x40>; /* wan port bitmap */
+ switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xc>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@5 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_0>;
+ label = "lan4";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan3";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan1";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&qca8081>;
+ label = "wan";
+};
+
+&wifi {
+ status = "okay";
+ qcom,ath11k-calibration-variant = "Dynalink-DL-WRX36";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
new file mode 100644
index 00000000000..8a5200b4ebf
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "prpl Foundation Haze";
+ compatible = "prpl,haze", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ /* Aliases are required by U-Boot to patch MAC addresses */
+ ethernet0 = &dp6_syn;
+ ethernet1 = &dp4;
+ ethernet2 = &dp3;
+ ethernet3 = &dp2;
+ label-mac-device = &dp6_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ wps-button {
+ label = "wps";
+ gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset-button {
+ label = "reset";
+ gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-state {
+ mdc-pins {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ button_pins: button-state {
+ wps-pins {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ rst-pins {
+ pins = "gpio44";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&blsp1_spi1 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "qcom,smem-part";
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+
+ qca8075_1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_2: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_3: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_4: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ aqr113c: ethernet-phy@5 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ vqmmc-supply = <&l11>;
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x1e>; /* lan port bitmap */
+ switch_wan_bmp = <0x60>; /* wan port bitmap */
+ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@4 {
+ port_id = <6>;
+ phy_address = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+/* Dummy LAN port */
+&dp1 {
+ status = "disabled";
+ phy-handle = <&qca8075_1>;
+ label = "lan4";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan2";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan1";
+};
+
+&dp6_syn {
+ status = "okay";
+ qcom,mactype = <1>;
+ phy-handle = <&aqr113c>;
+ label = "wan";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00020000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&pcie_qmp1 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+ bridge@1,0 {
+ reg = <0x00010000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "prpl-Haze";
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "prpl-Haze";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts
new file mode 100644
index 00000000000..5bfcdcc8ca3
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wax218.dts
@@ -0,0 +1,191 @@
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Netgear WAX218";
+ compatible = "netgear,wax218", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_power_amber;
+ led-failsafe = &led_power_amber;
+ led-running = &led_power_amber;
+ led-upgrade = &led_power_amber;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ /*
+ * Netgear's U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs"
+ * That fails to create a UBI block device, so add it here.
+ */
+ bootargs-append = " ubi.block=0,rootfs root=/dev/ubiblock0_1";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ led_spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+
+ led_gpio: led_gpio@0 {
+ compatible = "fairchild,74hc595";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ registers-number = <1>;
+ enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power_amber: led_power {
+ label = "amber:power";
+ gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_lan {
+ label = "blue:lan";
+ gpios = <&led_gpio 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_wlan_2g {
+ label = "blue:wlan2g";
+ gpios = <&led_gpio 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_wlan_5g {
+ label = "blue:wlan5g";
+ gpios = <&led_gpio 4 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x3e>;
+ switch_wan_bmp = <0x40>;
+ switch_mac_mode = <0x00>;
+ switch_mac_mode1 = <0xff>;
+ switch_mac_mode2 = <0x0f>;
+ bm_tick_mode = <0>;
+ tm_tick_mode = <0>;
+
+ qcom,port_phyinfo {
+ port@5 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+
+ qca8081_28: ethernet-phy@28 {
+ reg = <28>;
+ };
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&qca8081_28>;
+ label = "lan";
+ nvmem-cells = <&macaddr_ubootenv_ethaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "qcom,smem-part";
+
+ partition-0-appsblenv {
+ compatible = "fixed-partitions";
+ label = "0:appsblenv";
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ compatible = "u-boot,env";
+ label = "env-data";
+ reg = <0x0 0x40000>;
+
+ macaddr_ubootenv_ethaddr: ethaddr {};
+ };
+ };
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Netgear-WAX218";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts
new file mode 100644
index 00000000000..9779070725b
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8072-wpq873.dts
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright 2023 Nokia */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Compex WPQ873";
+ compatible = "compex,wpq873", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_power_blue;
+ led-failsafe = &led_power_red;
+ led-running = &led_system_green;
+ led-upgrade = &led_system_blue;
+ /* Aliases as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp6;
+ ethernet1 = &dp2;
+ ethernet2 = &dp3;
+ ethernet3 = &dp4;
+ label-mac-device = &dp6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_1";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power_red: power-red {
+ label = "red:power";
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led_power_blue: power-blue {
+ label = "blue:power";
+ gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led_system_red: system-red {
+ label = "red:system";
+ gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led_system_green: system-green {
+ label = "green:system";
+ gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led_system_blue: system-blue {
+ label = "blue:system";
+ gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ pins = "gpio0", "gpio2";
+ function = "blsp5_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ status = "okay";
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ button_pins: button_pins {
+ reset_button {
+ pins = "gpio66";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_spi1 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsblenv";
+ reg = <0x480000 0x10000>;
+ };
+
+ partition@490000 {
+ label = "0:appsbl";
+ reg = <0x490000 0xa0000>;
+ read-only;
+ };
+
+ partition@550000 {
+ label = "0:appsbl_1";
+ reg = <0x530000 0xa0000>;
+ read-only;
+ };
+
+ partition@610000 {
+ label = "0:art";
+ reg = <0x5d0000 0x40000>;
+ read-only;
+ };
+
+ partition@650000 {
+ label = "0:ethphyfw";
+ reg = <0x610000 0x80000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "rootfs";
+ reg = <0x0000000 0x3400000>;
+ };
+
+ partition@3400000 {
+ label = "0:wififw";
+ reg = <0x3400000 0x800000>;
+ read-only;
+ };
+
+ partition@3c00000 {
+ label = "rootfs_1";
+ reg = <0x3c00000 0x3400000>;
+ };
+
+ partition@7000000 {
+ label = "0:wififw_1";
+ reg = <0x7000000 0x800000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8081: ethernet-phy@28 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <28>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_lan_bmp = <0x3e>; /* lan port bitmap */
+ switch_wan_bmp = <0x40>; /* wan port bitmap */
+ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
+ switch_mac_mode1 = <0x0f>; /* mac mode for uniphy instance1*/
+ switch_mac_mode2 = <0x0f>; /* mac mode for uniphy instance2*/
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ qcom,port_phyinfo {
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@5 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan1";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan3";
+};
+
+&dp6 {
+ status = "okay";
+ phy-handle = <&qca8081>;
+ label = "wan";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00020000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&pcie_qmp1 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
+
+ bridge@1,0 {
+ reg = <0x00010000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Compex-WPQ873";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi
new file mode 100644
index 00000000000..dace4008b38
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-512m.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "ipq8074.dtsi"
+
+&tzapp_region {
+ reg = <0x0 0x4a400000 0x0 0x100000>;
+};
+
+&q6_region {
+ reg = <0x0 0x4b000000 0x0 0x3700000>;
+};
+
+&q6_etr_region {
+ reg = <0x0 0x4e700000 0x0 0x100000>;
+};
+
+&m3_dump_region {
+ reg = <0x0 0x4e800000 0x0 0x100000>;
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
new file mode 100644
index 00000000000..057d5920311
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <dt-bindings/thermal/thermal.h>
+#include "ipq8074-cpr-regulator.dtsi"
+
+&CPU0 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+
+&CPU1 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+
+&CPU2 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+
+&CPU3 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+&cpu0_thermal {
+ trips {
+ cpu0_passive: cpu-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_passive>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu1_thermal {
+ trips {
+ cpu1_passive: cpu-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_passive>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu2_thermal {
+ trips {
+ cpu2_passive: cpu-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_passive>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu3_thermal {
+ trips {
+ cpu3_passive: cpu-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_passive>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cluster_thermal {
+ trips {
+ cluster_passive: cluster-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cluster_passive>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi
new file mode 100644
index 00000000000..e351a2e759a
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-cpr-regulator.dtsi
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "pmp8074.dtsi"
+
+&soc {
+ apc_apm: apm@b111000 {
+ compatible = "qcom,ipq807x-apm";
+ reg = <0xb111000 0x1000>;
+ reg-names = "pm-apcc-glb";
+ qcom,apm-post-halt-delay = <0x2>;
+ qcom,apm-halt-clk-delay = <0x11>;
+ qcom,apm-resume-clk-delay = <0x10>;
+ qcom,apm-sel-switch-delay = <0x01>;
+ };
+
+ apc_cpr: cpr4-ctrl@b018000 {
+ compatible = "qcom,cpr4-ipq807x-apss-regulator";
+ reg = <0xb018000 0x4000>, <0xa4000 0x1000>, <0x0193d008 0x4>;
+ reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpr";
+ qcom,cpr-ctrl-name = "apc";
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-step-quot-init-min = <12>;
+ qcom,cpr-step-quot-init-max = <14>;
+ qcom,cpr-count-mode = <0>; /* All-at-once */
+ qcom,cpr-count-repeat = <14>;
+ qcom,cpr-down-error-step-limit = <1>;
+ qcom,cpr-up-error-step-limit = <1>;
+ qcom,apm-ctrl = <&apc_apm>;
+ qcom,apm-threshold-voltage = <848000>;
+ vdd-supply = <&s3>;
+ qcom,voltage-step = <8000>;
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <0>;
+ qcom,cpr-up-threshold = <4>;
+ qcom,cpr-down-threshold = <1>;
+
+ apc_vreg: regulator {
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <6>;
+ qcom,cpr-part-types = <2>;
+ qcom,cpr-parts-voltage = <1048000>;
+ qcom,cpr-parts-voltage-v2 = <992000>;
+ qcom,cpr-fuse-corners = <4>;
+ qcom,cpr-fuse-combos = <8>;
+ qcom,cpr-corners = <6>;
+ qcom,cpr-speed-bins = <1>;
+ qcom,cpr-speed-bin-corners = <6>;
+ qcom,cpr-corner-fmax-map = <1 3 5 6>;
+ qcom,allow-voltage-interpolation;
+ qcom,allow-quotient-interpolation;
+ qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+ qcom,cpr-voltage-ceiling =
+ <840000 904000 944000
+ 984000 992000 1064000>;
+ qcom,cpr-voltage-floor =
+ <592000 648000 712000
+ 744000 784000 848000>;
+ qcom,corner-frequencies =
+ <1017600000 1382400000 1651200000
+ 1843200000 1920000000 2208000000>;
+
+ /* TT/FF parts i.e. turbo L1 OL voltage < 1048 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 12000>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ /* SS parts i.e turbo L1 OL voltage >= 1048 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 20000 26000 0 20000>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ /* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ /* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1 =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 7000 36000 4000>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ /* v2 - FF parts i.e. turbo L1 OL voltage < 992 mV */
+ qcom,cpr-closed-loop-voltage-adjustment-v2-0 =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ /* v2 - SS/TT parts i.e turbo L1 OL voltage >= 992 mV */
+ qcom,cpr-closed-loop-voltage-adjustment-v2-1 =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 0 0 19000 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ qcom,cpr-ro-scaling-factor =
+ < 3970 4150 0 2280 2520 2470 2250 2280
+ 2390 2330 2530 2500 850 2900 2510 2170 >,
+ < 3970 4150 0 2280 2520 2470 2250 2280
+ 2390 2330 2530 2500 850 2900 2510 2170 >,
+ < 3970 4150 0 2280 2520 2470 2250 2280
+ 2390 2330 2530 2500 850 2900 2510 2170 >,
+ < 3970 4150 0 2280 2520 2470 2250 2280
+ 2390 2330 2530 2500 850 2900 2510 2170 >;
+
+ qcom,cpr-floor-to-ceiling-max-range =
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>,
+ < 40000 40000 40000 40000 40000 40000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ npu_cpr: npu-cpr {
+ compatible = "qcom,cpr3-ipq807x-npu-regulator";
+ reg = <0xa4000 0x1000>, <0x0193d008 0x4>;
+ reg-names = "fuse_base", "cpr_tcsr_reg";
+ qcom,cpr-ctrl-name = "npu";
+ vdd-supply = <&s4>;
+ qcom,voltage-step = <8000>;
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <1>;
+
+ npu_vreg: regulator {
+ regulator-name = "npu_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <3>;
+ qcom,cpr-part-types = <2>;
+ qcom,cpr-parts-voltage = <968000>;
+ qcom,cpr-parts-voltage-v2 = <832001>;
+ qcom,cpr-cold-temp-threshold-v2 = <30>;
+ qcom,cpr-fuse-corners = <2>;
+ qcom,cpr-fuse-combos = <1>;
+ qcom,cpr-corners = <2>;
+ qcom,cpr-speed-bins = <1>;
+ qcom,cpr-speed-bin-corners = <2>;
+ qcom,allow-voltage-interpolation;
+ qcom,cpr-corner-fmax-map = <1 2>;
+ qcom,cpr-voltage-ceiling =
+ <912000 992000>;
+ qcom,cpr-voltage-floor =
+ <752000 792000>;
+ qcom,corner-frequencies =
+ <1497600000 1689600000>;
+
+ /* TT/FF parts i.e. turbo OL voltage < 968 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
+ < 40000 40000>;
+
+ /* SS parts i.e turbo OL voltage >= 968 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
+ < 24000 24000>;
+
+ /* FF parts i.e. turbo OL voltage <= 832 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0=
+ <40000 40000>;
+
+ /* TT/SS parts i.e turbo OL voltage > 832 mV */
+ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1=
+ <40000 40000>;
+
+ /* FF parts i.e. turbo OL voltage <= 832 mV */
+ qcom,cpr-cold-temp-voltage-adjustment-v2-0 =
+ <0 0>;
+
+ /* TT/SS parts i.e turbo OL voltage > 832 mV */
+ qcom,cpr-cold-temp-voltage-adjustment-v2-1 =
+ <35000 27000>;
+ };
+ };
+ };
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
new file mode 100644
index 00000000000..129266c50d1
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+&clocks {
+ bias_pll_cc_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_nss_noc_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <416500000>;
+ #clock-cells = <0>;
+ };
+};
+
+&soc {
+ switch: ess-switch@3a000000 {
+ compatible = "qcom,ess-switch-ipq807x";
+ reg = <0x3a000000 0x1000000>;
+ switch_access_mode = "local bus";
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_inner_bmp = <0x80>; /*inner port bitmap*/
+ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>,
+ <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>,
+ <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_UNIPHY2_AHB_CLK>,
+ <&gcc GCC_UNIPHY2_SYS_CLK>,
+ <&gcc GCC_PORT1_MAC_CLK>,
+ <&gcc GCC_PORT2_MAC_CLK>,
+ <&gcc GCC_PORT3_MAC_CLK>,
+ <&gcc GCC_PORT4_MAC_CLK>,
+ <&gcc GCC_PORT5_MAC_CLK>,
+ <&gcc GCC_PORT6_MAC_CLK>,
+ <&gcc GCC_NSS_PPE_CLK>,
+ <&gcc GCC_NSS_PPE_CFG_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
+ <&gcc GCC_NSS_EDMA_CLK>,
+ <&gcc GCC_NSS_EDMA_CFG_CLK>,
+ <&gcc GCC_NSS_PPE_IPE_CLK>,
+ <&gcc GCC_NSS_PPE_BTQ_CLK>,
+ <&gcc GCC_MDIO_AHB_CLK>,
+ <&gcc GCC_NSS_NOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
+ <&gcc GCC_NSS_CRYPTO_CLK>,
+ <&gcc GCC_NSS_IMEM_CLK>,
+ <&gcc GCC_NSS_PTP_REF_CLK>,
+ <&gcc GCC_NSS_PORT1_RX_CLK>,
+ <&gcc GCC_NSS_PORT1_TX_CLK>,
+ <&gcc GCC_NSS_PORT2_RX_CLK>,
+ <&gcc GCC_NSS_PORT2_TX_CLK>,
+ <&gcc GCC_NSS_PORT3_RX_CLK>,
+ <&gcc GCC_NSS_PORT3_TX_CLK>,
+ <&gcc GCC_NSS_PORT4_RX_CLK>,
+ <&gcc GCC_NSS_PORT4_TX_CLK>,
+ <&gcc GCC_NSS_PORT5_RX_CLK>,
+ <&gcc GCC_NSS_PORT5_TX_CLK>,
+ <&gcc GCC_NSS_PORT6_RX_CLK>,
+ <&gcc GCC_NSS_PORT6_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
+ <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
+ <&gcc NSS_PORT5_RX_CLK_SRC>,
+ <&gcc NSS_PORT5_TX_CLK_SRC>;
+ clock-names = "cmn_ahb_clk", "cmn_sys_clk",
+ "uniphy0_ahb_clk", "uniphy0_sys_clk",
+ "uniphy1_ahb_clk", "uniphy1_sys_clk",
+ "uniphy2_ahb_clk", "uniphy2_sys_clk",
+ "port1_mac_clk", "port2_mac_clk",
+ "port3_mac_clk", "port4_mac_clk",
+ "port5_mac_clk", "port6_mac_clk",
+ "nss_ppe_clk", "nss_ppe_cfg_clk",
+ "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
+ "nss_edma_clk", "nss_edma_cfg_clk",
+ "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
+ "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
+ "gcc_nssnoc_snoc_clk",
+ "gcc_mem_noc_nss_axi_clk",
+ "gcc_nss_crypto_clk",
+ "gcc_nss_imem_clk",
+ "gcc_nss_ptp_ref_clk",
+ "nss_port1_rx_clk", "nss_port1_tx_clk",
+ "nss_port2_rx_clk", "nss_port2_tx_clk",
+ "nss_port3_rx_clk", "nss_port3_tx_clk",
+ "nss_port4_rx_clk", "nss_port4_tx_clk",
+ "nss_port5_rx_clk", "nss_port5_tx_clk",
+ "nss_port6_rx_clk", "nss_port6_tx_clk",
+ "uniphy0_port1_rx_clk",
+ "uniphy0_port1_tx_clk",
+ "uniphy0_port2_rx_clk",
+ "uniphy0_port2_tx_clk",
+ "uniphy0_port3_rx_clk",
+ "uniphy0_port3_tx_clk",
+ "uniphy0_port4_rx_clk",
+ "uniphy0_port4_tx_clk",
+ "uniphy0_port5_rx_clk",
+ "uniphy0_port5_tx_clk",
+ "uniphy1_port5_rx_clk",
+ "uniphy1_port5_tx_clk",
+ "uniphy2_port6_rx_clk",
+ "uniphy2_port6_tx_clk",
+ "nss_port5_rx_clk_src",
+ "nss_port5_tx_clk_src";
+ resets = <&gcc GCC_PPE_FULL_RESET>,
+ <&gcc GCC_UNIPHY0_SOFT_RESET>,
+ <&gcc GCC_UNIPHY0_XPCS_RESET>,
+ <&gcc GCC_UNIPHY1_SOFT_RESET>,
+ <&gcc GCC_UNIPHY1_XPCS_RESET>,
+ <&gcc GCC_UNIPHY2_SOFT_RESET>,
+ <&gcc GCC_UNIPHY2_XPCS_RESET>,
+ <&gcc GCC_NSSPORT1_RESET>,
+ <&gcc GCC_NSSPORT2_RESET>,
+ <&gcc GCC_NSSPORT3_RESET>,
+ <&gcc GCC_NSSPORT4_RESET>,
+ <&gcc GCC_NSSPORT5_RESET>,
+ <&gcc GCC_NSSPORT6_RESET>;
+ reset-names = "ppe_rst", "uniphy0_soft_rst",
+ "uniphy0_xpcs_rst", "uniphy1_soft_rst",
+ "uniphy1_xpcs_rst", "uniphy2_soft_rst",
+ "uniphy2_xpcs_rst", "nss_port1_rst",
+ "nss_port2_rst", "nss_port3_rst",
+ "nss_port4_rst", "nss_port5_rst",
+ "nss_port6_rst";
+ mdio-bus = <&mdio>;
+ status = "disabled";
+
+ port_scheduler_resource {
+ port@0 {
+ port_id = <0>;
+ ucast_queue = <0 143>;
+ mcast_queue = <256 271>;
+ l0sp = <0 35>;
+ l0cdrr = <0 47>;
+ l0edrr = <0 47>;
+ l1cdrr = <0 7>;
+ l1edrr = <0 7>;
+ };
+ port@1 {
+ port_id = <1>;
+ ucast_queue = <144 159>;
+ mcast_queue = <272 275>;
+ l0sp = <36 39>;
+ l0cdrr = <48 63>;
+ l0edrr = <48 63>;
+ l1cdrr = <8 11>;
+ l1edrr = <8 11>;
+ };
+ port@2 {
+ port_id = <2>;
+ ucast_queue = <160 175>;
+ mcast_queue = <276 279>;
+ l0sp = <40 43>;
+ l0cdrr = <64 79>;
+ l0edrr = <64 79>;
+ l1cdrr = <12 15>;
+ l1edrr = <12 15>;
+ };
+ port@3 {
+ port_id = <3>;
+ ucast_queue = <176 191>;
+ mcast_queue = <280 283>;
+ l0sp = <44 47>;
+ l0cdrr = <80 95>;
+ l0edrr = <80 95>;
+ l1cdrr = <16 19>;
+ l1edrr = <16 19>;
+ };
+ port@4 {
+ port_id = <4>;
+ ucast_queue = <192 207>;
+ mcast_queue = <284 287>;
+ l0sp = <48 51>;
+ l0cdrr = <96 111>;
+ l0edrr = <96 111>;
+ l1cdrr = <20 23>;
+ l1edrr = <20 23>;
+ };
+ port@5 {
+ port_id = <5>;
+ ucast_queue = <208 223>;
+ mcast_queue = <288 291>;
+ l0sp = <52 55>;
+ l0cdrr = <112 127>;
+ l0edrr = <112 127>;
+ l1cdrr = <24 27>;
+ l1edrr = <24 27>;
+ };
+ port@6 {
+ port_id = <6>;
+ ucast_queue = <224 239>;
+ mcast_queue = <292 295>;
+ l0sp = <56 59>;
+ l0cdrr = <128 143>;
+ l0edrr = <128 143>;
+ l1cdrr = <28 31>;
+ l1edrr = <28 31>;
+ };
+ port@7 {
+ port_id = <7>;
+ ucast_queue = <240 255>;
+ mcast_queue = <296 299>;
+ l0sp = <60 63>;
+ l0cdrr = <144 159>;
+ l0edrr = <144 159>;
+ l1cdrr = <32 35>;
+ l1edrr = <32 35>;
+ };
+ };
+ port_scheduler_config {
+ port@0 {
+ port_id = <0>;
+ l1scheduler {
+ group@0 {
+ sp = <0 1>; /*L0 SPs*/
+ /*cpri cdrr epri edrr*/
+ cfg = <0 0 0 0>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ /*unicast queues*/
+ ucast_queue = <0 4 8>;
+ /*multicast queues*/
+ mcast_queue = <256 260>;
+ /*sp cpri cdrr epri edrr*/
+ cfg = <0 0 0 0 0>;
+ };
+ group@1 {
+ ucast_queue = <1 5 9>;
+ mcast_queue = <257 261>;
+ cfg = <0 1 1 1 1>;
+ };
+ group@2 {
+ ucast_queue = <2 6 10>;
+ mcast_queue = <258 262>;
+ cfg = <0 2 2 2 2>;
+ };
+ group@3 {
+ ucast_queue = <3 7 11>;
+ mcast_queue = <259 263>;
+ cfg = <0 3 3 3 3>;
+ };
+ };
+ };
+ port@1 {
+ port_id = <1>;
+ l1scheduler {
+ group@0 {
+ sp = <36>;
+ cfg = <0 8 0 8>;
+ };
+ group@1 {
+ sp = <37>;
+ cfg = <1 9 1 9>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <144>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <272>;
+ mcast_loop_pri = <4>;
+ cfg = <36 0 48 0 48>;
+ };
+ };
+ };
+ port@2 {
+ port_id = <2>;
+ l1scheduler {
+ group@0 {
+ sp = <40>;
+ cfg = <0 12 0 12>;
+ };
+ group@1 {
+ sp = <41>;
+ cfg = <1 13 1 13>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <160>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <276>;
+ mcast_loop_pri = <4>;
+ cfg = <40 0 64 0 64>;
+ };
+ };
+ };
+ port@3 {
+ port_id = <3>;
+ l1scheduler {
+ group@0 {
+ sp = <44>;
+ cfg = <0 16 0 16>;
+ };
+ group@1 {
+ sp = <45>;
+ cfg = <1 17 1 17>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <176>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <280>;
+ mcast_loop_pri = <4>;
+ cfg = <44 0 80 0 80>;
+ };
+ };
+ };
+ port@4 {
+ port_id = <4>;
+ l1scheduler {
+ group@0 {
+ sp = <48>;
+ cfg = <0 20 0 20>;
+ };
+ group@1 {
+ sp = <49>;
+ cfg = <1 21 1 21>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <192>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <284>;
+ mcast_loop_pri = <4>;
+ cfg = <48 0 96 0 96>;
+ };
+ };
+ };
+ port@5 {
+ port_id = <5>;
+ l1scheduler {
+ group@0 {
+ sp = <52>;
+ cfg = <0 24 0 24>;
+ };
+ group@1 {
+ sp = <53>;
+ cfg = <1 25 1 25>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <208>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <288>;
+ mcast_loop_pri = <4>;
+ cfg = <52 0 112 0 112>;
+ };
+ };
+ };
+ port@6 {
+ port_id = <6>;
+ l1scheduler {
+ group@0 {
+ sp = <56>;
+ cfg = <0 28 0 28>;
+ };
+ group@1 {
+ sp = <57>;
+ cfg = <1 29 1 29>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <224>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <292>;
+ mcast_loop_pri = <4>;
+ cfg = <56 0 128 0 128>;
+ };
+ };
+ };
+ port@7 {
+ port_id = <7>;
+ l1scheduler {
+ group@0 {
+ sp = <60>;
+ cfg = <0 32 0 32>;
+ };
+ group@1 {
+ sp = <61>;
+ cfg = <1 33 1 33>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <240>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <296>;
+ cfg = <60 0 144 0 144>;
+ };
+ };
+ };
+ };
+ };
+
+ ess-uniphy@7a00000 {
+ compatible = "qcom,ess-uniphy";
+ reg = <0x7a00000 0x30000>;
+ uniphy_access_mode = "local bus";
+ };
+
+ edma: edma@3ab00000 {
+ compatible = "qcom,edma";
+ reg = <0x3ab00000 0x76900>;
+ reg-names = "edma-reg-base";
+ qcom,txdesc-ring-start = <23>;
+ qcom,txdesc-rings = <1>;
+ qcom,txcmpl-ring-start = <7>;
+ qcom,txcmpl-rings = <1>;
+ qcom,rxfill-ring-start = <7>;
+ qcom,rxfill-rings = <1>;
+ qcom,rxdesc-ring-start = <15>;
+ qcom,rxdesc-rings = <1>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&gcc GCC_EDMA_HW_RESET>;
+ reset-names = "edma_rst";
+ status = "disabled";
+ };
+
+ dp1: dp1 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <1>;
+ reg = <0x3a001000 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp2: dp2 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <2>;
+ reg = <0x3a001200 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp3: dp3 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <3>;
+ reg = <0x3a001400 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp4: dp4 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <4>;
+ reg = <0x3a001600 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp5: dp5 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <5>;
+ reg = <0x3a001800 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp6: dp6 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <6>;
+ reg = <0x3a001a00 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp5_syn: dp5-syn {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <5>;
+ reg = <0x3a003000 0x3fff>;
+ qcom,mactype = <1>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp6_syn: dp6-syn {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <6>;
+ reg = <0x3a007000 0x3fff>;
+ qcom,mactype = <1>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
new file mode 100644
index 00000000000..37af7bbc1f7
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <dt-bindings/thermal/thermal.h>
+#include "ipq8074-cpr-regulator.dtsi"
+
+&CPU0 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+
+&CPU1 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+
+&CPU2 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+
+&CPU3 {
+ cpu-supply = <&apc_vreg>;
+ voltage-tolerance = <1>;
+};
+&cpu0_thermal {
+ trips {
+ cpu0_passive_low: cpu-passive-low {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_passive_high: cpu-passive-high {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_passive_low>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu0_passive_high>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu1_thermal {
+ trips {
+ cpu1_passive_low: cpu-passive-low {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_passive_high: cpu-passive-high {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_passive_low>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu1_passive_high>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu2_thermal {
+ trips {
+ cpu2_passive_low: cpu-passive-low {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_passive_high: cpu-passive-high {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_passive_low>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu2_passive_high>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cpu3_thermal {
+ trips {
+ cpu3_passive_low: cpu-passive-low {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_passive_high: cpu-passive-high {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_passive_low>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu3_passive_high>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&cluster_thermal {
+ trips {
+ cluster_passive_low: cluster-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cluster_passive_high: cluster-passive-high {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cluster_passive_low>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cluster_passive_high>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
new file mode 100644
index 00000000000..d113b233ecf
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
@@ -0,0 +1,445 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
+ * Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
+ */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+
+
+/ {
+ model = "Zyxel NBG7815";
+ compatible = "zyxel,nbg7815", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
+ /* Alias as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp1;
+ label-mac-device = &dp1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <0>;
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsbl";
+ reg = <0x480000 0xc0000>;
+ read-only;
+ };
+
+ partition@540000 {
+ label = "0:appsbl_1";
+ reg = <0x540000 0xc0000>;
+ read-only;
+ };
+
+ partition@600000 {
+ compatible = "u-boot,env";
+ label = "0:appsblenv";
+ reg = <0x600000 0x10000>;
+
+ macaddr_lan: ethaddr {
+ #nvmem-cell-cells = <1>;
+ };
+ };
+
+ partition@610000 {
+ label = "0:art";
+ reg = <0x610000 0x40000>;
+ read-only;
+ };
+
+ partition@650000 {
+ label = "0:ethphyfw";
+ reg = <0x650000 0x80000>;
+ read-only;
+ };
+
+ partition@6d0000 {
+ label = "0:crt";
+ reg = <0x6d0000 0x10000>;
+ read-only;
+ };
+
+ partition@6e0000 {
+ label = "dual_flag";
+ reg = <0x6e0000 0x10000>;
+ };
+
+ partition@6f0000 {
+ label = "reserved";
+ reg = <0x6f0000 0x110000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ qca8075_1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_2: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_3: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_4: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8081: ethernet-phy@4{
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ };
+
+ aqr113c: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x3e>;
+ switch_wan_bmp = <0x40>;
+ switch_mac_mode = <0x0>;
+ switch_mac_mode1 = <0xf>;
+ switch_mac_mode2 = <0xd>;
+ bm_tick_mode = <0>;
+ tm_tick_mode = <0>;
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+
+ port@1 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@2 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@3 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@4 {
+ port_id = <5>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+
+ port@5 {
+ port_id = <6>;
+ ethernet-phy-ieee802.3-c45;
+ phy_address = <8>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_lan 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_lan 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_lan 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_lan 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8081>;
+ label = "wan";
+ nvmem-cells = <&macaddr_lan 1>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&aqr113c>;
+ label = "10g";
+ nvmem-cells = <&macaddr_lan 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&blsp1_i2c2 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ tmp103@70 {
+ compatible = "ti,tmp103";
+ reg = <0x70>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+ /* unstable, problem with the hs400 > h200 speed switch */
+ /delete-property/ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ vqmmc-supply = <&l11>;
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
+};
diff --git a/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
new file mode 100644
index 00000000000..32386dc93e0
--- /dev/null
+++ b/target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-wxr-5950ax12.dts
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Buffalo WXR-5950AX12";
+ compatible = "buffalo,wxr-5950ax12", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_power_white;
+ led-failsafe = &led_power_red;
+ led-running = &led_power_white;
+ led-upgrade = &led_power_white;
+ label-mac-device = &dp5_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " ubi.mtd=user_property root=/dev/ubiblock1_0";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "white:router";
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_WHITE>;
+ };
+
+ led-1 {
+ label = "red:router";
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led_power_red: led-2 {
+ label = "red:power";
+ gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ led_power_white: led-3 {
+ label = "white:power";
+ gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ led-4 {
+ label = "white:internet";
+ gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_WHITE>;
+ };
+
+ led-5 {
+ label = "red:internet";
+ gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led-6 {
+ label = "red:wireless";
+ gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN;
+ };
+
+ led-7 {
+ label = "white:wireless";
+ gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_WLAN;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ /*
+ * mode: 3x position switch
+ *
+ * - ROUTER
+ * - AP
+ * - WB (Wireless Bridge)
+ */
+ ap {
+ label = "mode-ap";
+ gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ bridge {
+ label = "mode-wb";
+ gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_1>;
+ };
+
+ /*
+ * op: 2x position switch
+ *
+ * - AUTO
+ * - MANUAL (select Router/AP/WB manually)
+ */
+ manual {
+ label = "op-manual";
+ gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_2>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ reg_usb_vbus: regulator-5v-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "qcom,smem-part";
+
+ partition-0-appsblenv {
+ compatible = "fixed-partitions";
+ label = "0:appsblenv";
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ compatible = "u-boot,env";
+ label = "env-data";
+ reg = <0x0 0x40000>;
+
+ macaddr_appsblenv_ethaddr: ethaddr {
+ };
+ };
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ /*
+ * RESET pins of phy chips
+ *
+ * WXR-5950AX12 has 2x RESET pins for QCA8075 and AQR113C.
+ * The pin of QCA8075 is for the chip and not phys in the chip, the
+ * pin of AQR113C is for 2x chips. So both pins are not appropriate
+ * to declare them as reset-gpios in phy nodes.
+ * Multiple entries in reset-gpios of mdio may not be supported, but
+ * leave the following as-is to show that the those reset pin exists.
+ */
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>, /* QCA8075 RESET */
+ <&tlmm 63 GPIO_ACTIVE_LOW>; /* AQR113C RESET (2x) */
+
+ aqr113c_1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+
+ aqr113c_2: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x8>;
+ };
+
+ qca8075_1: ethernet-phy@18 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x18>;
+ };
+
+ qca8075_2: ethernet-phy@19 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x19>;
+ };
+
+ qca8075_3: ethernet-phy@1a {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1a>;
+ };
+
+ qca8075_4: ethernet-phy@1b {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1b>;
+ };
+
+ qca8075_5: ethernet-phy@1c {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1c>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x3e>;
+ switch_wan_bmp = <0x40>;
+ switch_mac_mode = <0xb>;
+ switch_mac_mode1 = <0xd>;
+ switch_mac_mode2 = <0xd>;
+ bm_tick_mode = <0>;
+ tm_tick_mode = <0>;
+
+ qcom,port_phyinfo {
+ port@0 {
+ port_id = <1>;
+ phy_address = <0x18>;
+ };
+
+ port@1 {
+ port_id = <2>;
+ phy_address = <0x19>;
+ };
+
+ port@2 {
+ port_id = <3>;
+ phy_address = <0x1a>;
+ };
+
+ port@3 {
+ port_id = <4>;
+ phy_address = <0x1b>;
+ };
+
+ port@4 {
+ port_id = <5>;
+ ethernet-phy-ieee802.3-c45;
+ phy_address = <0x0>;
+ };
+
+ port@5 {
+ port_id = <6>;
+ ethernet-phy-ieee802.3-c45;
+ phy_address = <0x8>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_appsblenv_ethaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_appsblenv_ethaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_appsblenv_ethaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp5_syn {
+ status = "okay";
+ phy-handle = <&aqr113c_1>;
+ label = "wan";
+ nvmem-cells = <&macaddr_appsblenv_ethaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-handle = <&aqr113c_2>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_appsblenv_ethaddr>;
+ nvmem-cell-names = "mac-address";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+
+ vbus-supply = <&reg_usb_vbus>;
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Buffalo-WXR-5950AX12";
+};
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-19 11:18:30 +0000