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| author | Felix Fietkau <nbd@openwrt.org> | 2014-09-02 16:44:40 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2014-09-02 16:44:40 +0000 |
| commit | d032df6d9e5eb8b1b722aa23222f8577e178b95a (patch) | |
| tree | ba0b9eb67ab03ce731d44c7e918d26844cc9de22 /target/linux/omap/patches-3.12/408-ARM-dts-am33xx-Add-mcasp0-and-mcasp1-device-tree-ent.patch | |
| parent | 02111e915c514abae6344afdd08bf0e2e099987c (diff) | |
| download | upstream-d032df6d9e5eb8b1b722aa23222f8577e178b95a.tar.gz upstream-d032df6d9e5eb8b1b722aa23222f8577e178b95a.tar.bz2 upstream-d032df6d9e5eb8b1b722aa23222f8577e178b95a.zip | |
cns3xxx: support isolated PCI interrupts on newer Laguna PCBs
The cns3xxx uses irq61 for pcie0_intr which in the case of a PCIe-to-PCI
bridge ends up combining INTA/B/C/D on a single ARM CPU interrupt. This is
not optimal when you have multiple cores. To overcome this limitation an
enhancement was made on newer Laguna PCB's that support miniPCI cards
to route the INTA/B/C/D signals to unique external ARM CPU interrupts which
can help balance CPU core utilization and in some cases increase overall
system performance or responsiveness.
For more details see:
http://trac.gateworks.com/wiki/multicoreprocessing#PCIInterruptsteering
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42400 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/omap/patches-3.12/408-ARM-dts-am33xx-Add-mcasp0-and-mcasp1-device-tree-ent.patch')
0 files changed, 0 insertions, 0 deletions