diff options
author | Pawel Dembicki <paweldembicki@gmail.com> | 2023-04-12 10:43:43 +0200 |
---|---|---|
committer | Christian Lamparter <chunkeey@gmail.com> | 2023-05-14 00:08:35 +0200 |
commit | 95d5a99537a587103976120de0b0ba4d27e07d62 (patch) | |
tree | 5a350e425fe9b5e16f117356425d4fa2fef6de5f /target/linux/mpc85xx/files | |
parent | 749237967a122a40465b65c7e9eb6924d8fe09c4 (diff) | |
download | upstream-95d5a99537a587103976120de0b0ba4d27e07d62.tar.gz upstream-95d5a99537a587103976120de0b0ba4d27e07d62.tar.bz2 upstream-95d5a99537a587103976120de0b0ba4d27e07d62.zip |
mpc85xx: add support for Aerohive BR200-WP
The following adds the Aerohive BR200-WP router to OpenWrt under
the mpc85xx/p1010 subtarget.
Hardware:
- SoC: Freescale P1011
- NOR: Intel JS28F512M29EWH 64MB
- Memory: 2x Nanya NT5TU64M16GG-AC 128MB (Total of 256MB)
- 2.4GHz WiFi: Atheros AR9390-AL1A
- Eth1: Atheros AR8035-A PoE
- 2x LEDs
- 1x Button
- PoE PSE
Flashing:
1. Hook into UART (9600 baud) and enter U-Boot. You may need to enter a
password of administrator or AhNf?d@ta06 if prompted.
2. Once in U-Boot, tftp boot the initramfs image:
dhcp; setenv serverip 192.168.1.3;
tftpboot 0x2004000 openwrt-mpc85xx-p1010-aerohive_br200-wp-initramfs-kernel.bin;
bootm 0x2004000;
3. Once booted, scp over the sysupgrade file and sysupgrade the device
to flash LEDE to the NOR.
Note:
MAC assigns are taken from stock firmware:
Name MAC addr Mode State Chan(Width) VLAN Radio Hive SSID
-------- -------------- -------- ----- ----------- ---- ---------- ---------- ---------
Mgt0 08ea:44XX:XXc0 - U - 1 - hive0 -
Eth0 08ea:44XX:XXc0 wan U - - - - -
Eth1 08ea:44XX:XXc2 access D - - - hive0 -
Eth2 08ea:44XX:XXc3 access D - - - hive0 -
Eth3 08ea:44XX:XXc4 access D - - - hive0 -
Eth4 08ea:44XX:XXc5 access D - - - hive0 -
Wifi0 08ea:44XX:XXd0 access U 1(20MHz) - radio_ng0 - -
Wifi0.1 08ea:44XX:XXd4 access D 1(20MHz) - radio_ng0 hive0 -
Note2:
PoE PSE could be managed with `realtek-poe` package. Example port
config:
config port
option enable '1'
option id '4'
option name 'lan2'
option poe_plus '0'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan1'
option poe_plus '0'
option priority '1'
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
(switch@0 -> switch@10, Device's quickstart says LEDs are
amber and white => add function+color properties but keep
labels around, use pr_info)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Diffstat (limited to 'target/linux/mpc85xx/files')
-rw-r--r-- | target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts | 373 | ||||
-rw-r--r-- | target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c | 82 |
2 files changed, 455 insertions, 0 deletions
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts new file mode 100644 index 0000000000..a4bc10ff38 --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aerohive BR200-WP Device Tree Source + * + * Based on: Aerohive HiveAP-330 Device Tree Source + * + * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com> + * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com> + */ + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +/include/ "fsl/p1020si-pre.dtsi" + +/ { + model = "Aerohive BR200-WP"; + compatible = "aerohive,br200-wp"; + + chosen { + bootargs = "console=ttyS0,9600"; + bootargs-override = "console=ttyS0,9600 noinitrd"; + }; + + aliases { + led-boot = &led_attention; + led-failsafe = &led_attention; + led-running = &led_status; + led-upgrade = &led_status; + label-mac-device = &enet0; + }; + + memory { + device_type = "memory"; + }; + + cpus { + /delete-property/ PowerPC,P1020@1; /* P1011 have one core only */ + }; + + board_lbc: lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + ranges = <0x0 0x0 0x0 0xec000000 0x4000000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x40000>; + label = "dtb"; + }; + + partition@40000 { + reg = <0x40000 0x40000>; + label = "initramfs"; + }; + + partition@80000 { + reg = <0x80000 0x27c0000>; + label = "rootfs"; + }; + + partition@2840000 { + reg = <0x2840000 0x800000>; + label = "kernel"; + }; + + partition@3040000 { + reg = <0x3040000 0xec0000>; + label = "stock-jffs2"; + read-only; + }; + + partition@3f00000 { + reg = <0x3f00000 0x20000>; + label = "hw-info"; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_hwinfo_0: macaddr@0 { + reg = <0x0 0x6>; + }; + }; + + partition@3f20000 { + reg = <0x3f20000 0x20000>; + label = "boot-info"; + read-only; + }; + + partition@3f40000 { + reg = <0x3f40000 0x20000>; + label = "boot-info-backup"; + read-only; + }; + + partition@3f60000 { + reg = <0x3f60000 0x20000>; + label = "u-boot-env"; + }; + + partition@3f80000 { + reg = <0x3f80000 0x80000>; + label = "u-boot"; + read-only; + }; + + firmware@0 { + reg = <0x0 0x3040000>; + label = "firmware"; + }; + }; + }; + }; + + board_soc: soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + + mdio@24000 { + + phy_port1: phy@0 { + reg = <0>; + }; + + phy_port2: phy@1 { + reg = <1>; + }; + + phy_port3: phy@2 { + reg = <2>; + }; + + phy_port4: phy@3 { + reg = <3>; + }; + + phy_port5: phy@4 { + reg = <4>; + }; + + switch@10 { + compatible = "qca,qca8327"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&phy_port1>; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&phy_port2>; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&phy_port3>; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <4>; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-handle = <&phy_port4>; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <5>; + }; + + port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&phy_port5>; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + ethernet = <&enet0>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; + + mdio@25000 { + status = "disabled"; + }; + + mdio@26000 { + status = "disabled"; + }; + + enet0: ethernet@b0000 { + status = "okay"; + phy-connection-type = "rgmii-id"; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@b1000 { + status = "disabled"; + }; + + enet2: ethernet@b2000 { + status = "disabled"; + }; + + gpio0: gpio-controller@fc00 { + }; + + usb@22000 { + phy_type = "ulpi"; + dr_mode = "host"; + }; + + usb@23000 { + status = "disabled"; + }; + }; + + pci0: pcie@ffe09000 { + status = "disabled"; + }; + + pci1: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>; + + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + + pcie@0 { + ranges = <0x2000000 0x0 0xc0000000 + 0x2000000 0x0 0xc0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + + ath9k: wifi@0,0 { + reg = <0x0000 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + nvmem-cells = <&macaddr_hwinfo_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <16>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_attention: led-0 { + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + label = "amber:status"; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_STATUS; + }; + + led_status: led-1 { + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + label = "white:status"; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_STATUS; + }; + }; + + buttons { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; +}; + +/include/ "fsl/p1020si-post.dtsi" + +/ { + chosen { + linux,stdout-path = "/soc@ffe00000/serial@4500"; + }; + + cpus { + PowerPC,P1020@0 { + i-cache-sets = <0x80>; + i-cache-size = <0x8000>; + i-cache-block-size = <0x20>; + d-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-block-size = <0x20>; + clock-frequency = <0x2756cd00>; + bus-frequency = <0x13ab6680>; + timebase-frequency = <0x2756cd0>; + }; + }; + + memory { + reg = <0x00 0x00 0x00 0x10000000>; + }; + + localbus@ffe05000 { + bus-frequency = <0x13ab668>; + }; + + soc@ffe00000 { + bus-frequency = <0x13ab6680>; + + serial@4500 { + clock-frequency = <0x13ab6680>; + }; + + serial@4600 { + clock-frequency = <0x13ab6680>; + }; + }; + + pcie@ffe09000 { + clock-frequency = <0x1fca055>; + }; + + pcie@ffe0a000 { + clock-frequency = <0x1fca055>; + }; +}; diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c new file mode 100644 index 0000000000..23fd11a5c6 --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/br200-wp.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Aerohive BR200-WP Board Setup + * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com> + * + * Based on: + * hiveap-330.c: + * Aerohive HiveAP-330 Board Setup + * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com> + */ + +#include <linux/stddef.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/of_platform.h> + +#include <asm/time.h> +#include <asm/machdep.h> +#include <asm/pci-bridge.h> +#include <mm/mmu_decl.h> +#include <asm/prom.h> +#include <asm/udbg.h> +#include <asm/mpic.h> + +#include <sysdev/fsl_soc.h> +#include <sysdev/fsl_pci.h> +#include "smp.h" + +#include "mpc85xx.h" + +void __init br200_wp_pic_init(void) +{ + struct mpic *mpic; + + mpic = mpic_alloc(NULL, 0, + MPIC_BIG_ENDIAN | + MPIC_SINGLE_DEST_CPU, + 0, 256, " OpenPIC "); + + BUG_ON(mpic == NULL); + mpic_init(mpic); +} + +/* + * Setup the architecture + */ +static void __init br200_wp_setup_arch(void) +{ + if (ppc_md.progress) + ppc_md.progress("br200_wp_setup_arch()", 0); + + fsl_pci_assign_primary(); + + pr_info("br200-wp board from Aerohive\n"); +} + +machine_arch_initcall(br200_wp, mpc85xx_common_publish_devices); + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init br200_wp_probe(void) +{ + if (of_machine_is_compatible("aerohive,br200-wp")) + return 1; + return 0; +} + +define_machine(br200_wp) { + .name = "P1020 RDB", + .probe = br200_wp_probe, + .setup_arch = br200_wp_setup_arch, + .init_IRQ = br200_wp_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, + .pcibios_fixup_phb = fsl_pcibios_fixup_phb, +#endif + .get_irq = mpic_get_irq, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; 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