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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2017-03-12 12:30:30 +0100 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-03-12 15:45:50 +0100 |
| commit | 9a065fcfecbf344812a92dbd9b28298da7ef2b74 (patch) | |
| tree | c01ee36c2d11f00cd1f66953e100c1316bc6453e /target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch | |
| parent | f5d403488ed62bb7f0e0017b02890b4d72240a55 (diff) | |
| download | upstream-9a065fcfecbf344812a92dbd9b28298da7ef2b74.tar.gz upstream-9a065fcfecbf344812a92dbd9b28298da7ef2b74.tar.bz2 upstream-9a065fcfecbf344812a92dbd9b28298da7ef2b74.zip | |
kernel: update kernel 4.9 to 4.9.14
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch')
| -rw-r--r-- | target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch b/target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch index 2ff6990d10..a22cb9941f 100644 --- a/target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch +++ b/target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch @@ -193,7 +193,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> #include <dt-bindings/clock/mt2701-clk.h> -@@ -465,6 +466,10 @@ +@@ -465,6 +466,10 @@ static const char * const cpu_parents[] "mmpll" }; @@ -204,7 +204,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> static const struct mtk_composite top_muxes[] __initconst = { MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3, INVALID_MUX_GATE_BIT), -@@ -677,6 +682,9 @@ +@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(str mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), clk_data); @@ -224,7 +224,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> #include <dt-bindings/clock/mt8173-clk.h> -@@ -525,6 +526,25 @@ +@@ -525,6 +526,25 @@ static const char * const i2s3_b_ck_pare "apll2_div5" }; @@ -250,7 +250,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> static const struct mtk_composite top_muxes[] __initconst = { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), -@@ -948,6 +968,9 @@ +@@ -948,6 +968,9 @@ static void __init mtk_infrasys_init(str clk_data); mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); |