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author | INAGAKI Hiroshi <musashino.open@gmail.com> | 2021-04-23 18:32:11 +0900 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2022-05-21 22:27:01 +0100 |
commit | 58b3b557b629f6a2046414e0e1b39189d918133f (patch) | |
tree | f87ed3c4b85f06c01946915a5343aa622ec69cd8 /target/linux/mediatek/dts | |
parent | e01b1c22dfb669abb0ad14c83ec9b3e35ff3d15c (diff) | |
download | upstream-58b3b557b629f6a2046414e0e1b39189d918133f.tar.gz upstream-58b3b557b629f6a2046414e0e1b39189d918133f.tar.bz2 upstream-58b3b557b629f6a2046414e0e1b39189d918133f.zip |
mediatek: mt7622: add support for ELECOM WRC-X3200GST3
ELECOM WRC-X3200GST3 is a 2.4/5 GHz band 11ax (Wi-Fi 6) router, based on
MT7622B.
Specifications:
- SoC : MediaTek MT7622B
- RAM : DDR3 512 MiB (Nanya NT5CC256M16ER-EK)
- Flash : SPI-NAND 128 MiB (Winbond W25N01GVZEIG)
- WLAN : 2.4/5 GHz 4T4R
- 2.4 GHz : MediaTek MT7622B (SoC)
- 5 GHz : MediaTek MT7915A
- Ethernet : 5x 10/100/1000 Mbps
- Switch : MediaTek MT7531
- LEDs/Keys : 6x/4x (2x buttons, 1x slide-switch)
- UART : through-hole on PCB
- J19: 3.3V, GND, TX, RX from power jack side
- 115200n8
- Power : 12 VDC, 1.5 A
Flash instruction using factory image:
1. Boot WRC-X3200GST3 normally with "Router" mode
2. Access to "http://192.168.2.1/" and open firmware update page
("ファームウェア更新")
3. Select the OpenWrt factory image and click apply ("適用") button
4. Wait ~120 seconds to complete flashing
MAC Addresses:
LAN : 04:AB:18:xx:xx:77 (Factory, 0x7FFF4 (hex))
WAN : 04:AB:18:xx:xx:78 (Factory, 0x7FFFA (hex))
2.4 GHz: 04:AB:18:xx:xx:79 (Factory, 0x4 (hex))
5 GHz : 04:AB:18:xx:xx:7A (none)
Note:
- currently, there is no "phy1tpt" trigger for 5 GHz wlan (MT7915) in
"trigger" file of LEDs, use "phy1radio" trigger instead
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Diffstat (limited to 'target/linux/mediatek/dts')
-rw-r--r-- | target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts | 436 |
1 files changed, 436 insertions, 0 deletions
diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts new file mode 100644 index 0000000000..fdbcbc18bc --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + model = "ELECOM WRC-X3200GST3"; + compatible = "elecom,wrc-x3200gst3", "mediatek,mt7622"; + + aliases { + serial0 = &uart0; + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_green; + label-mac-device = &wan; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + memory { + reg = <0 0x40000000 0 0x1f000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "red:wps"; + gpios = <&pio 47 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_WPS; + }; + + led_power_red: led-1 { + label = "red:power"; + gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_POWER; + function-enumerator = <1>; + }; + + led_power_green: led-2 { + label = "green:power"; + gpios = <&pio 49 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + function-enumerator = <2>; + }; + + led-3 { + label = "blue:power"; + gpios = <&pio 50 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_POWER; + function-enumerator = <3>; + }; + + led-4 { + label = "white:wlan2g"; + gpios = <&pio 85 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_WLAN; + function-enumerator = <1>; + linux,default-trigger = "phy0tpt"; + }; + + led-5 { + label = "white:wlan5g"; + gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_WLAN; + function-enumerator = <2>; + linux,default-trigger = "phy1radio"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + + ap { + label = "ap"; + gpios = <&pio 42 GPIO_ACTIVE_LOW>; + linux,code = <BTN_0>; + linux,input-type = <EV_SW>; + }; + + router { + label = "router"; + gpios = <&pio 43 GPIO_ACTIVE_LOW>; + linux,code = <BTN_1>; + linux,input-type = <EV_SW>; + }; + + wps { + label = "wps"; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WPS_BUTTON>; + }; + }; +}; + +&cpu0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&cpu1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + pwm7_pins: pwm1-2-pins { + mux { + function = "pwm"; + groups = "pwm_ch7_2"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + + conf-cmd-data { + pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI", + "SPI_MISO", "SPI_CS"; + drive-strength = <16>; + bias-pull-up; + }; + + conf-clk { + pins = "SPI_CLK"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-connection-type = "2500base-x"; + + nvmem-cells = <&macaddr_factory_7fff4>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + wan: port@0 { + reg = <0>; + label = "wan"; + + nvmem-cells = <&macaddr_factory_7fffa>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan1"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-remap-range = <0x0 0x8c0000>, + <0x1bc0000 0x30c0000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; + + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; + + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x80000>; + read-only; + }; + + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x100000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + + macaddr_factory_7fff4: macaddr@7fff4 { + reg = <0x7fff4 0x6>; + }; + + macaddr_factory_7fffa: macaddr@7fffa { + reg = <0x7fffa 0x6>; + }; + }; + + partition@2c0000 { + label = "kernel"; + reg = <0x2c0000 0x600000>; + }; + + partition@8c0000 { + label = "ubi"; + reg = <0x8c0000 0x1300000>; + }; + + partition@1bc0000 { + label = "tm_pattern"; + reg = <0x1bc0000 0x500000>; + read-only; + }; + + partition@20c0000 { + label = "tm_key"; + reg = <0x20c0000 0x100000>; + read-only; + }; + + partition@21c0000 { + label = "user_data"; + reg = <0x21c0000 0xf00000>; + read-only; + }; + + partition@30c0000 { + label = "reserved"; + reg = <0x30c0000 0x4f40000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&slot0 { + status = "okay"; + + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x5000>; + ieee80211-freq-limit = <5000000 6000000>; + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; |