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| author | Furong Xu <xfr@outlook.com> | 2022-12-16 21:13:37 +0800 |
|---|---|---|
| committer | Chuanhong Guo <gch981213@gmail.com> | 2022-12-16 21:42:02 +0800 |
| commit | 335c1e7cfdfd477a1106ca05c96ff8949ecd953f (patch) | |
| tree | ca4707664e0e4ab8a5d7e6083e23f009c006a8ca /target/linux/mediatek/dts | |
| parent | 9e2c01e4a6a5c9b7c77fde90306af5f441ef2cb0 (diff) | |
| download | upstream-335c1e7cfdfd477a1106ca05c96ff8949ecd953f.tar.gz upstream-335c1e7cfdfd477a1106ca05c96ff8949ecd953f.tar.bz2 upstream-335c1e7cfdfd477a1106ca05c96ff8949ecd953f.zip | |
mediatek: enable sel_clk for spi-mt65xx
Without explicitly enabling sel_clk, clk_disable_unused() will disable
it when boot is done, causing CPU hang on SPI1 register access on MT7986.
Explicitly enable sel_clk to make SPI1 functional.
Signed-off-by: Furong Xu <xfr@outlook.com>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/mediatek/dts')
0 files changed, 0 insertions, 0 deletions