diff options
| author | Yangbo Lu <yangbo.lu@nxp.com> | 2020-04-10 10:47:05 +0800 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2020-05-07 12:53:06 +0200 |
| commit | cddd4591404fb4c53dc0b3c0b15b942cdbed4356 (patch) | |
| tree | 392c1179de46b0f804e3789edca19069b64e6b44 /target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch | |
| parent | d1d2c0b5579ea4f69a42246c9318539d61ba1999 (diff) | |
| download | upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.tar.gz upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.tar.bz2 upstream-cddd4591404fb4c53dc0b3c0b15b942cdbed4356.zip | |
layerscape: add patches-5.4
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/
For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.
The patches are sorted into the following categories:
301-arch-xxxx
302-dts-xxxx
303-core-xxxx
701-net-xxxx
801-audio-xxxx
802-can-xxxx
803-clock-xxxx
804-crypto-xxxx
805-display-xxxx
806-dma-xxxx
807-gpio-xxxx
808-i2c-xxxx
809-jailhouse-xxxx
810-keys-xxxx
811-kvm-xxxx
812-pcie-xxxx
813-pm-xxxx
814-qe-xxxx
815-sata-xxxx
816-sdhc-xxxx
817-spi-xxxx
818-thermal-xxxx
819-uart-xxxx
820-usb-xxxx
821-vfio-xxxx
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch b/target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch new file mode 100644 index 0000000000..a08edfa1e4 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/812-pcie-0018-PCI-mobiveil-Add-workaround-for-unsupported-request-.patch @@ -0,0 +1,51 @@ +From 7cc1ca9e3a87027dbe6598a0c50cb466fc5861e4 Mon Sep 17 00:00:00 2001 +From: Xiaowei Bao <xiaowei.bao@nxp.com> +Date: Tue, 22 Jan 2019 19:19:30 +0800 +Subject: [PATCH] PCI: mobiveil: Add workaround for unsupported request error + +Errata: unsupported request error on inbound posted write +transaction, PCIe controller reports advisory error instead +of uncorrectable error message to RC. + +Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> +Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> +--- + drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++ + drivers/pci/controller/mobiveil/pcie-mobiveil.h | 4 ++++ + 2 files changed, 17 insertions(+) + +--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c ++++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c +@@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct mo + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep); + int win_idx; + u8 bar; ++ u32 val; ++ ++ /* ++ * Errata: unsupported request error on inbound posted write ++ * transaction, PCIe controller reports advisory error instead ++ * of uncorrectable error message to RC. ++ * workaround: set the bit20(unsupported_request_Error_severity) with ++ * value 1 in uncorrectable_Error_Severity_Register, make the ++ * unsupported request error generate the fatal error. ++ */ ++ val = csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY); ++ val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT; ++ csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY); + + ep->bar_num = PCIE_LX2_BAR_NUM; + +--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h ++++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h +@@ -123,6 +123,10 @@ + #define GPEX_BAR_SIZE_UDW 0x4DC + #define GPEX_BAR_SELECT 0x4E0 + ++#define CFG_UNCORRECTABLE_ERROR_SEVERITY 0x10c ++#define UNSUPPORTED_REQUEST_ERROR_SHIFT 20 ++#define CFG_UNCORRECTABLE_ERROR_MASK 0x108 ++ + /* starting offset of INTX bits in status register */ + #define PAB_INTX_START 5 + |