layerscape: add patches-5.4

Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 73 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-5.4/802-can-0016-can-flexcan-flexcan_irq-add-support-for-TX-mailbox-i.patch b/target/linux/layerscape/patches-5.4/802-can-0016-can-flexcan-flexcan_irq-add-support-for-TX-mailbox-i.patch
new file mode 100644
index 0000000000..5fb96f4512
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/802-can-0016-can-flexcan-flexcan_irq-add-support-for-TX-mailbox-i.patch
@@ -0,0 +1,73 @@
+From 57d3edbdcfee9b677452744bba5c4f08b476872a Mon Sep 17 00:00:00 2001
+From: Marc Kleine-Budde <mkl@pengutronix.de>
+Date: Fri, 1 Mar 2019 15:38:05 +0100
+Subject: [PATCH] can: flexcan: flexcan_irq(): add support for TX mailbox in
+ iflag1
+
+The flexcan IP core has up to 64 mailboxes, each one has a corresponding
+interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
+imask1 or imask2 registers.
+
+The driver will always use the last mailbox for TX, which falls into the iflag2
+register.
+
+To support CANFD the payload size has to increase to 64 bytes and the number of
+mailboxes will decrease so much that the TX mailbox will be handled in the
+iflag1 register.
+
+This patch add support to handle the TX mailbox independent whether it's
+in iflag1 or iflag2 by introducing th flexcan_read_reg_iflag_tx()
+function, similar to flexcan_read_reg_iflag_rx(), for the read path.
+
+For the write path the function flexcan_write64() is added.
+
+Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
+---
+ drivers/net/can/flexcan.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/can/flexcan.c
++++ b/drivers/net/can/flexcan.c
+@@ -791,11 +791,24 @@ static inline u64 flexcan_read64_mask(st
+ 	return reg & mask;
+ }
+ 
++static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
++{
++	if (upper_32_bits(val))
++		priv->write(upper_32_bits(val), addr - 4);
++	if (lower_32_bits(val))
++		priv->write(lower_32_bits(val), addr);
++}
++
+ static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
+ {
+ 	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
+ }
+ 
++static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
++{
++	return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
++}
++
+ static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
+ {
+ 	return container_of(offload, struct flexcan_priv, offload);
+@@ -932,7 +945,7 @@ static irqreturn_t flexcan_irq(int irq,
+ 		}
+ 	}
+ 
+-	reg_iflag_tx = (u64)priv->read(&regs->iflag2) << 32;
++	reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
+ 
+ 	/* transmission complete interrupt */
+ 	if (reg_iflag_tx & priv->tx_mask) {
+@@ -947,7 +960,7 @@ static irqreturn_t flexcan_irq(int irq,
+ 		/* after sending a RTR frame MB is in RX mode */
+ 		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
+ 			    &priv->tx_mb->can_ctrl);
+-		priv->write(priv->tx_mask >> 32, &regs->iflag2);
++		flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
+ 		netif_wake_queue(dev);
+ 	}
+