layerscape: add patches-5.4

Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 108 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-5.4/801-audio-0033-MLK-13946-3-ASoC-fsl_sai-fix-the-xMR-setting.patch b/target/linux/layerscape/patches-5.4/801-audio-0033-MLK-13946-3-ASoC-fsl_sai-fix-the-xMR-setting.patch
new file mode 100644
index 0000000000..c353ba4ae4
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/801-audio-0033-MLK-13946-3-ASoC-fsl_sai-fix-the-xMR-setting.patch
@@ -0,0 +1,108 @@
+From 9d00118e0ac420d3bf6e266a0fbfd28135cbadb8 Mon Sep 17 00:00:00 2001
+From: Shengjiu Wang <shengjiu.wang@nxp.com>
+Date: Thu, 12 Oct 2017 14:01:19 +0800
+Subject: [PATCH] MLK-13946-3: ASoC: fsl_sai: fix the xMR setting
+
+When there is multi data line enabled, the xMR setting is
+wrong if according to the channel number. which should
+according to the slot number
+
+Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
+---
+ sound/soc/fsl/fsl_sai.c | 28 ++++++++++++++++++++++++++--
+ sound/soc/fsl/fsl_sai.h | 12 ++++++++++++
+ 2 files changed, 38 insertions(+), 2 deletions(-)
+
+--- a/sound/soc/fsl/fsl_sai.c
++++ b/sound/soc/fsl/fsl_sai.c
+@@ -80,7 +80,7 @@ static struct fsl_sai_soc_data fsl_sai_i
+ 
+ static struct fsl_sai_soc_data fsl_sai_imx8qm = {
+ 	.imx = true,
+-	.dataline = 0x3,
++	.dataline = 0xf,
+ 	.fifos = 1,
+ 	.fifo_depth = 64,
+ 	.flags = 0,
+@@ -571,7 +571,7 @@ static int fsl_sai_hw_params(struct snd_
+ 	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset),
+ 			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
+ 			   FSL_SAI_CR5_FBT_MASK, val_cr5);
+-	regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
++	regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << slots) - 1));
+ 
+ 	return 0;
+ }
+@@ -858,11 +858,23 @@ static bool fsl_sai_readable_reg(struct
+ 	switch (reg) {
+ 	case FSL_SAI_TFR0:
+ 	case FSL_SAI_TFR1:
++	case FSL_SAI_TFR2:
++	case FSL_SAI_TFR3:
++	case FSL_SAI_TFR4:
++	case FSL_SAI_TFR5:
++	case FSL_SAI_TFR6:
++	case FSL_SAI_TFR7:
+ 	case FSL_SAI_TMR:
+ 	case FSL_SAI_RDR0:
+ 	case FSL_SAI_RDR1:
+ 	case FSL_SAI_RFR0:
+ 	case FSL_SAI_RFR1:
++	case FSL_SAI_RFR2:
++	case FSL_SAI_RFR3:
++	case FSL_SAI_RFR4:
++	case FSL_SAI_RFR5:
++	case FSL_SAI_RFR6:
++	case FSL_SAI_RFR7:
+ 	case FSL_SAI_RMR:
+ 		return true;
+ 	default:
+@@ -881,8 +893,20 @@ static bool fsl_sai_volatile_reg(struct
+ 	switch (reg) {
+ 	case FSL_SAI_TFR0:
+ 	case FSL_SAI_TFR1:
++	case FSL_SAI_TFR2:
++	case FSL_SAI_TFR3:
++	case FSL_SAI_TFR4:
++	case FSL_SAI_TFR5:
++	case FSL_SAI_TFR6:
++	case FSL_SAI_TFR7:
+ 	case FSL_SAI_RFR0:
+ 	case FSL_SAI_RFR1:
++	case FSL_SAI_RFR2:
++	case FSL_SAI_RFR3:
++	case FSL_SAI_RFR4:
++	case FSL_SAI_RFR5:
++	case FSL_SAI_RFR6:
++	case FSL_SAI_RFR7:
+ 	case FSL_SAI_RDR0:
+ 	case FSL_SAI_RDR1:
+ 		return true;
+--- a/sound/soc/fsl/fsl_sai.h
++++ b/sound/soc/fsl/fsl_sai.h
+@@ -24,6 +24,12 @@
+ #define FSL_SAI_TDR1    0x24 /* SAI Transmit Data */
+ #define FSL_SAI_TFR0    0x40 /* SAI Transmit FIFO */
+ #define FSL_SAI_TFR1    0x44 /* SAI Transmit FIFO */
++#define FSL_SAI_TFR2    0x48 /* SAI Transmit FIFO */
++#define FSL_SAI_TFR3    0x4C /* SAI Transmit FIFO */
++#define FSL_SAI_TFR4    0x50 /* SAI Transmit FIFO */
++#define FSL_SAI_TFR5    0x54 /* SAI Transmit FIFO */
++#define FSL_SAI_TFR6    0x58 /* SAI Transmit FIFO */
++#define FSL_SAI_TFR7    0x5C /* SAI Transmit FIFO */
+ #define FSL_SAI_TFR	0x40 /* SAI Transmit FIFO */
+ #define FSL_SAI_TMR	0x60 /* SAI Transmit Mask */
+ #define FSL_SAI_RCSR(offset) (0x80 + offset) /* SAI Receive Control */
+@@ -36,6 +42,12 @@
+ #define FSL_SAI_RDR1    0xa4 /* SAI Receive Data */
+ #define FSL_SAI_RFR0    0xc0 /* SAI Receive FIFO */
+ #define FSL_SAI_RFR1    0xc4 /* SAI Receive FIFO */
++#define FSL_SAI_RFR2    0xc8 /* SAI Receive FIFO */
++#define FSL_SAI_RFR3    0xcc /* SAI Receive FIFO */
++#define FSL_SAI_RFR4    0xd0 /* SAI Receive FIFO */
++#define FSL_SAI_RFR5    0xd4 /* SAI Receive FIFO */
++#define FSL_SAI_RFR6    0xd8 /* SAI Receive FIFO */
++#define FSL_SAI_RFR7    0xdc /* SAI Receive FIFO */
+ #define FSL_SAI_RMR	0xe0 /* SAI Receive Mask */
+ 
+ #define FSL_SAI_xCSR(tx, off)	(tx ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off))