layerscape: add patches-5.4

Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 893 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-5.4/302-dts-0113-arm64-dts-fsl-ls1028a-qds-Add-overlays-for-various-s.patch b/target/linux/layerscape/patches-5.4/302-dts-0113-arm64-dts-fsl-ls1028a-qds-Add-overlays-for-various-s.patch
new file mode 100644
index 0000000000..0d1b23c85b
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/302-dts-0113-arm64-dts-fsl-ls1028a-qds-Add-overlays-for-various-s.patch
@@ -0,0 +1,893 @@
+From d2333a40b00ba5fb5b9731f96ca663036f781411 Mon Sep 17 00:00:00 2001
+From: Alex Marginean <alexandru.marginean@nxp.com>
+Date: Tue, 7 Jan 2020 14:48:20 +0200
+Subject: [PATCH] arm64: dts: fsl-ls1028a-qds: Add overlays for various serdes
+ protocols
+
+Adds overlays for various serdes protocols on LS1028A QDS board using
+different PHY cards.  These should be applied at boot, based on serdes
+configuration.  If no overlay is applied, only the RGMII interface on
+the QDS is available in Linux.
+
+Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile             |   6 ++
+ .../boot/dts/freescale/fsl-ls1028a-qds-13bb.dts    | 100 +++++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi   |  20 -----
+ .../boot/dts/freescale/fsl-ls1028a-qds-65bb.dts    |  94 +++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi   |  20 -----
+ .../boot/dts/freescale/fsl-ls1028a-qds-7777.dts    |  73 +++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi   |  56 ------------
+ .../boot/dts/freescale/fsl-ls1028a-qds-85bb.dts    |  93 +++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-899b.dts    |  66 ++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi   |  19 ----
+ .../boot/dts/freescale/fsl-ls1028a-qds-9999.dts    |  71 +++++++++++++++
+ .../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi   |  57 ------------
+ .../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi   |  61 -------------
+ .../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi   |  57 ------------
+ arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts  |   3 -
+ 15 files changed, 503 insertions(+), 293 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
+ delete mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
+
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -6,6 +6,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
+@@ -0,0 +1,100 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree fragment for LS1028A QDS board, serdes 13bb
++ *
++ * Copyright 2019 NXP
++ *
++ * Requires a LS1028A QDS board with lane B rework.
++ * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
++ * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&mdio_slot1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			slot1_sgmii: ethernet-phy@2 {
++				/* AQR112 */
++				reg = <0x2>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&enetc_port0>;
++		__overlay__ {
++			phy-handle = <&slot1_sgmii>;
++			phy-mode = "usxgmii";
++		};
++	};
++
++	fragment@2 {
++		target = <&mdio_slot2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* 4 ports on AQR412 */
++			slot2_qxgmii0: ethernet-phy@0 {
++				reg = <0x0>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++
++			slot2_qxgmii1: ethernet-phy@1 {
++				reg = <0x1>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++
++			slot2_qxgmii2: ethernet-phy@2 {
++				reg = <0x2>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++
++			slot2_qxgmii3: ethernet-phy@3 {
++				reg = <0x3>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&mscc_felix_ports>;
++		__overlay__ {
++			port@0 {
++				status = "okay";
++				phy-handle = <&slot2_qxgmii0>;
++				phy-mode = "usxgmii";
++				managed = "in-band-status";
++			};
++
++			port@1 {
++				status = "okay";
++				phy-handle = <&slot2_qxgmii1>;
++				phy-mode = "usxgmii";
++				managed = "in-band-status";
++			};
++
++			port@2 {
++				status = "okay";
++				phy-handle = <&slot2_qxgmii2>;
++				phy-mode = "usxgmii";
++				managed = "in-band-status";
++			};
++
++			port@3 {
++				status = "okay";
++				phy-handle = <&slot2_qxgmii3>;
++				phy-mode = "usxgmii";
++				managed = "in-band-status";
++			};
++		};
++	};
++};
++
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
++++ /dev/null
+@@ -1,20 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes 1xxx
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot1 {
+-	slot1_sgmii: ethernet-phy@2 {
+-		/* AQR112 */
+-		reg = <0x2>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-};
+-
+-&enetc_port0 {
+-	phy-handle = <&slot1_sgmii>;
+-	phy-connection-type = "usxgmii";
+-};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
+@@ -0,0 +1,94 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree fragment for LS1028A QDS board, serdes 69xx
++ *
++ * Copyright 2019 NXP
++ *
++ * Requires a LS1028A QDS board with lane B rework.
++ * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&mdio_slot1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			slot1_sgmii: ethernet-phy@2 {
++				/* AQR112 */
++				reg = <0x2>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&enetc_port0>;
++		__overlay__ {
++			phy-handle = <&slot1_sgmii>;
++			phy-mode = "2500base-x";
++		};
++	};
++
++	fragment@2 {
++		target = <&mdio_slot2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* 4 ports on VSC8514 */
++			slot2_qsgmii0: ethernet-phy@8 {
++				reg = <0x8>;
++			};
++
++			slot2_qsgmii1: ethernet-phy@9 {
++				reg = <0x9>;
++			};
++
++			slot2_qsgmii2: ethernet-phy@a {
++				reg = <0xa>;
++			};
++
++			slot2_qsgmii3: ethernet-phy@b {
++				reg = <0xb>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&mscc_felix_ports>;
++		__overlay__ {
++			port@0 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii0>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++
++			port@1 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii1>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++
++			port@2 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii2>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++
++			port@3 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii3>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
++++ /dev/null
+@@ -1,20 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes 6xxx
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot1 {
+-	slot1_sgmii: ethernet-phy@2 {
+-		/* AQR112 */
+-		reg = <0x2>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-};
+-
+-&enetc_port0 {
+-	phy-handle = <&slot1_sgmii>;
+-	phy-connection-type = "2500base-x";
+-};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
+@@ -0,0 +1,73 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree fragment for LS1028A QDS board, serdes 7777
++ *
++ * Copyright 2019 NXP
++ *
++ * Requires a LS1028A QDS board without lane B rework.
++ * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
++ * disabled, plugged in slot 1.
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&mdio_slot1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* 4 ports on AQR412 */
++			slot1_sxgmii0: ethernet-phy@0 {
++				reg = <0x0>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++
++			slot1_sxgmii1: ethernet-phy@1 {
++				reg = <0x1>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++
++			slot1_sxgmii2: ethernet-phy@2 {
++				reg = <0x2>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++
++			slot1_sxgmii3: ethernet-phy@3 {
++				reg = <0x3>;
++				compatible = "ethernet-phy-ieee802.3-c45";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&mscc_felix_ports>;
++		__overlay__ {
++			port@0 {
++				status = "okay";
++				phy-handle = <&slot1_sxgmii0>;
++				phy-mode = "2500base-x";
++			};
++
++			port@1 {
++				status = "okay";
++				phy-handle = <&slot1_sxgmii1>;
++				phy-mode = "2500base-x";
++			};
++
++			port@2 {
++				status = "okay";
++				phy-handle = <&slot1_sxgmii2>;
++				phy-mode = "2500base-x";
++			};
++
++			port@3 {
++				status = "okay";
++				phy-handle = <&slot1_sxgmii3>;
++				phy-mode = "2500base-x";
++			};
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
++++ /dev/null
+@@ -1,56 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes 9999
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot1 {
+-	slot1_sxgmii0: ethernet-phy@0 {
+-		reg = <0x0>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-
+-	slot1_sxgmii1: ethernet-phy@1 {
+-		reg = <0x1>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-
+-	slot1_sxgmii2: ethernet-phy@2 {
+-		reg = <0x2>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-
+-	slot1_sxgmii3: ethernet-phy@3 {
+-		reg = <0x3>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-};
+-
+-/* l2switch ports */
+-&mscc_felix_ports {
+-	port@0 {
+-		status = "okay";
+-		phy-handle = <&slot1_sxgmii0>;
+-		phy-mode = "2500base-x";
+-	};
+-
+-	port@1 {
+-		status = "okay";
+-		phy-handle = <&slot1_sxgmii1>;
+-		phy-mode = "2500base-x";
+-	};
+-
+-	port@2 {
+-		status = "okay";
+-		phy-handle = <&slot1_sxgmii2>;
+-		phy-mode = "2500base-x";
+-	};
+-
+-	port@3 {
+-		status = "okay";
+-		phy-handle = <&slot1_sxgmii3>;
+-		phy-mode = "2500base-x";
+-	};
+-};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
+@@ -0,0 +1,93 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree fragment for LS1028A QDS board, serdes 85bb
++ *
++ * Copyright 2019 NXP
++ *
++ * Requires a LS1028A QDS board with lane B rework.
++ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&mdio_slot1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			slot1_sgmii: ethernet-phy@1c {
++				/* 1st port on VSC8234 */
++				reg = <0x1c>;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&enetc_port0>;
++		__overlay__ {
++			phy-handle = <&slot1_sgmii>;
++			phy-mode = "sgmii";
++		};
++	};
++
++	fragment@2 {
++		target = <&mdio_slot2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* 4 ports on VSC8514 */
++			slot2_qsgmii0: ethernet-phy@8 {
++				reg = <0x8>;
++			};
++
++			slot2_qsgmii1: ethernet-phy@9 {
++				reg = <0x9>;
++			};
++
++			slot2_qsgmii2: ethernet-phy@a {
++				reg = <0xa>;
++			};
++
++			slot2_qsgmii3: ethernet-phy@b {
++				reg = <0xb>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&mscc_felix_ports>;
++		__overlay__ {
++			port@0 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii0>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++
++			port@1 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii1>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++
++			port@2 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii2>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++
++			port@3 {
++				status = "okay";
++				phy-handle = <&slot2_qsgmii3>;
++				phy-mode = "qsgmii";
++				managed = "in-band-status";
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
+@@ -0,0 +1,66 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree fragment for LS1028A QDS board, serdes 85xx
++ *
++ * Copyright 2019 NXP
++ *
++ * Requires a LS1028A QDS board without lane B rework.
++ * Requires a SCH-24801 card in slot 1.
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&mdio_slot1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* VSC8234 */
++			slot1_sgmii0: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++
++			slot1_sgmii1: ethernet-phy@1d {
++				reg = <0x1d>;
++			};
++
++			slot1_sgmii2: ethernet-phy@1e {
++				reg = <0x1e>;
++			};
++
++			slot1_sgmii3: ethernet-phy@1f {
++				reg = <0x1f>;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&enetc_port0>;
++		__overlay__ {
++			phy-handle = <&slot1_sgmii0>;
++			phy-mode = "sgmii";
++		};
++	};
++
++	fragment@2 {
++		target = <&mscc_felix_ports>;
++		__overlay__ {
++			port@1 {
++				status = "okay";
++				phy-handle = <&slot1_sgmii1>;
++				phy-mode = "sgmii";
++				managed = "in-band-status";
++			};
++
++			port@2 {
++				status = "okay";
++				phy-handle = <&slot1_sgmii2>;
++				phy-mode = "sgmii";
++				managed = "in-band-status";
++			};
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
++++ /dev/null
+@@ -1,19 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes 8xxx
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot1 {
+-	slot1_sgmii: ethernet-phy@1c {
+-		/* 1st port on VSC8234 */
+-		reg = <0x1c>;
+-	};
+-};
+-
+-&enetc_port0 {
+-	phy-handle = <&slot1_sgmii>;
+-	phy-connection-type = "sgmii";
+-};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
+@@ -0,0 +1,71 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree fragment for LS1028A QDS board, serdes 85xx
++ *
++ * Copyright 2019 NXP
++ *
++ * Requires a LS1028A QDS board without lane B rework.
++ * Requires a SCH-24801 card in slot 1.
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&mdio_slot1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			/* VSC8234 */
++			slot1_sgmii0: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++
++			slot1_sgmii1: ethernet-phy@1d {
++				reg = <0x1d>;
++			};
++
++			slot1_sgmii2: ethernet-phy@1e {
++				reg = <0x1e>;
++			};
++
++			slot1_sgmii3: ethernet-phy@1f {
++				reg = <0x1f>;
++			};
++		};
++	};
++	fragment@1 {
++		target = <&mscc_felix_ports>;
++		__overlay__ {
++			port@0 {
++				status = "okay";
++				phy-handle = <&slot1_sgmii0>;
++				phy-mode = "sgmii";
++				managed = "in-band-status";
++			};
++
++			port@1 {
++				status = "okay";
++				phy-handle = <&slot1_sgmii1>;
++				phy-mode = "sgmii";
++				managed = "in-band-status";
++			};
++
++			port@2 {
++				status = "okay";
++				phy-handle = <&slot1_sgmii2>;
++				phy-mode = "sgmii";
++				managed = "in-band-status";
++			};
++
++			port@3 {
++				status = "okay";
++				phy-handle = <&slot1_sgmii3>;
++				phy-mode = "sgmii";
++				managed = "in-band-status";
++			};
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
++++ /dev/null
+@@ -1,57 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes 9999
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot1 {
+-	/* VSC8234 */
+-	slot1_sgmii0: ethernet-phy@1c {
+-		reg = <0x1c>;
+-	};
+-
+-	slot1_sgmii1: ethernet-phy@1d {
+-		reg = <0x1d>;
+-	};
+-
+-	slot1_sgmii2: ethernet-phy@1e {
+-		reg = <0x1e>;
+-	};
+-
+-	slot1_sgmii3: ethernet-phy@1f {
+-		reg = <0x1f>;
+-	};
+-};
+-
+-/* l2switch ports */
+-&mscc_felix_ports {
+-	port@0 {
+-		status = "okay";
+-		phy-handle = <&slot1_sgmii0>;
+-		phy-mode = "sgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@1 {
+-		status = "okay";
+-		phy-handle = <&slot1_sgmii1>;
+-		phy-mode = "sgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@2 {
+-		status = "okay";
+-		phy-handle = <&slot1_sgmii2>;
+-		phy-mode = "sgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@3 {
+-		status = "okay";
+-		phy-handle = <&slot1_sgmii3>;
+-		phy-mode = "sgmii";
+-		managed = "in-band-status";
+-	};
+-};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
++++ /dev/null
+@@ -1,61 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes x3xx
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot2 {
+-	/* 4 ports on AQR412 */
+-	slot2_qxgmii0: ethernet-phy@0 {
+-		reg = <0x0>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-
+-	slot2_qxgmii1: ethernet-phy@1 {
+-		reg = <0x1>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-
+-	slot2_qxgmii2: ethernet-phy@2 {
+-		reg = <0x2>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-
+-	slot2_qxgmii3: ethernet-phy@3 {
+-		reg = <0x3>;
+-		compatible = "ethernet-phy-ieee802.3-c45";
+-	};
+-};
+-
+-/* l2switch ports */
+-&mscc_felix_ports {
+-	port@0 {
+-		status = "okay";
+-		phy-handle = <&slot2_qxgmii0>;
+-		phy-mode = "usxgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@1 {
+-		status = "okay";
+-		phy-handle = <&slot2_qxgmii1>;
+-		phy-mode = "usxgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@2 {
+-		status = "okay";
+-		phy-handle = <&slot2_qxgmii2>;
+-		phy-mode = "usxgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@3 {
+-		status = "okay";
+-		phy-handle = <&slot2_qxgmii3>;
+-		phy-mode = "usxgmii";
+-		managed = "in-band-status";
+-	};
+-};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
++++ /dev/null
+@@ -1,57 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-/*
+- * Device Tree Include file for LS1028A QDS board, serdes x5xx
+- *
+- * Copyright 2019 NXP
+- *
+- */
+-
+-&mdio_slot2 {
+-	/* 4 ports on VSC8514 */
+-	slot2_qsgmii0: ethernet-phy@8 {
+-		reg = <0x8>;
+-	};
+-
+-	slot2_qsgmii1: ethernet-phy@9 {
+-		reg = <0x9>;
+-	};
+-
+-	slot2_qsgmii2: ethernet-phy@a {
+-		reg = <0xa>;
+-	};
+-
+-	slot2_qsgmii3: ethernet-phy@b {
+-		reg = <0xb>;
+-	};
+-};
+-
+-/* l2switch ports */
+-&mscc_felix_ports {
+-	port@0 {
+-		status = "okay";
+-		phy-handle = <&slot2_qsgmii0>;
+-		phy-mode = "qsgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@1 {
+-		status = "okay";
+-		phy-handle = <&slot2_qsgmii1>;
+-		phy-mode = "qsgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@2 {
+-		status = "okay";
+-		phy-handle = <&slot2_qsgmii2>;
+-		phy-mode = "qsgmii";
+-		managed = "in-band-status";
+-	};
+-
+-	port@3 {
+-		status = "okay";
+-		phy-handle = <&slot2_qsgmii3>;
+-		phy-mode = "qsgmii";
+-		managed = "in-band-status";
+-	};
+-};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+@@ -276,6 +276,3 @@
+ 	lane-mapping = <0x4e>;
+ 	status = "okay";
+ };
+-
+-#include "fsl-ls1028a-qds-8xxx.dtsi"
+-#include "fsl-ls1028a-qds-x5xx.dtsi"