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authorYangbo Lu <yangbo.lu@nxp.com>2017-09-27 15:31:31 +0800
committerJohn Crispin <john@phrozen.org>2017-10-07 23:13:23 +0200
commit8fdda1cc1033e2bd0d048188af5167faffbf9b38 (patch)
treebe12aa762b013e30476e2bd784398a0b802bbc71 /target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch
parent19951bbf57da87093f7bde25bad41571fbdaf4d9 (diff)
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layerscape: add linux 4.9 support
This patch is to add linux 4.9 support for layerscape. All these kernel patches are from NXP LSDK 1709 release. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch')
-rw-r--r--target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch412
1 files changed, 412 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch b/target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch
new file mode 100644
index 0000000000..e45d2635fd
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch
@@ -0,0 +1,412 @@
+From c0e4767d3b26f21e5043fe2d15a24a1958de766e Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 25 Sep 2017 10:17:28 +0800
+Subject: [PATCH] mtd: support layerscape
+
+This is a integrated patch for layerscape ifc-nor-nand support.
+
+Signed-off-by: Alison Wang <b18965@freescale.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/memory/Kconfig | 2 +-
+ drivers/memory/fsl_ifc.c | 263 ++++++++++++++++++++++++++++++++++++++++
+ drivers/mtd/maps/physmap_of.c | 4 +
+ drivers/mtd/nand/Kconfig | 2 +-
+ drivers/mtd/nand/fsl_ifc_nand.c | 5 +-
+ include/linux/fsl_ifc.h | 7 ++
+ 6 files changed, 280 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
+index 4b4c0c3c..820f5590 100644
+--- a/drivers/memory/Kconfig
++++ b/drivers/memory/Kconfig
+@@ -115,7 +115,7 @@ config FSL_CORENET_CF
+
+ config FSL_IFC
+ bool
+- depends on FSL_SOC || ARCH_LAYERSCAPE
++ depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
+
+ config JZ4780_NEMC
+ bool "Ingenic JZ4780 SoC NEMC driver"
+diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c
+index 1b182b11..10d2a5f8 100644
+--- a/drivers/memory/fsl_ifc.c
++++ b/drivers/memory/fsl_ifc.c
+@@ -24,6 +24,7 @@
+ #include <linux/compiler.h>
+ #include <linux/sched.h>
+ #include <linux/spinlock.h>
++#include <linux/delay.h>
+ #include <linux/types.h>
+ #include <linux/slab.h>
+ #include <linux/io.h>
+@@ -37,6 +38,8 @@
+
+ struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+ EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
++#define FSL_IFC_V1_3_0 0x01030000
++#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
+
+ /*
+ * convert_ifc_address - convert the base address
+@@ -311,6 +314,261 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
+ return ret;
+ }
+
++#ifdef CONFIG_PM_SLEEP
++/* save ifc registers */
++static int fsl_ifc_suspend(struct device *dev)
++{
++ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
++ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
++ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
++ __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
++ gpcm_evter_intr_en;
++ uint32_t ifc_bank, i;
++
++ ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
++ if (!ctrl->saved_gregs)
++ return -ENOMEM;
++ ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
++ if (!ctrl->saved_rregs)
++ return -ENOMEM;
++
++ cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
++ nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
++ nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
++ gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
++
++/* IFC interrupts disabled */
++
++ ifc_out32(0x0, &fcm->cm_evter_intr_en);
++ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
++ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
++ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
++
++ if (ctrl->saved_gregs) {
++ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
++ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
++ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
++ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
++ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
++ ctrl->saved_gregs->amask_cs[ifc_bank].amask =
++ ifc_in32(&fcm->amask_cs[ifc_bank].amask);
++ ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
++ ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
++ ctrl->saved_gregs->csor_cs[ifc_bank].csor =
++ ifc_in32(&fcm->csor_cs[ifc_bank].csor);
++ for (i = 0; i < 4; i++) {
++ ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
++ ifc_in32(
++ &fcm->ftim_cs[ifc_bank].ftim[i]);
++ }
++ }
++
++ ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
++ ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
++ ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
++ ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
++ ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
++ }
++
++ if (ctrl->saved_rregs) {
++ /* IFC controller NAND machine registers */
++ ctrl->saved_rregs->ifc_nand.ncfgr =
++ ifc_in32(&runtime->ifc_nand.ncfgr);
++ ctrl->saved_rregs->ifc_nand.nand_fcr0 =
++ ifc_in32(&runtime->ifc_nand.nand_fcr0);
++ ctrl->saved_rregs->ifc_nand.nand_fcr1 =
++ ifc_in32(&runtime->ifc_nand.nand_fcr1);
++ ctrl->saved_rregs->ifc_nand.row0 =
++ ifc_in32(&runtime->ifc_nand.row0);
++ ctrl->saved_rregs->ifc_nand.row1 =
++ ifc_in32(&runtime->ifc_nand.row1);
++ ctrl->saved_rregs->ifc_nand.col0 =
++ ifc_in32(&runtime->ifc_nand.col0);
++ ctrl->saved_rregs->ifc_nand.col1 =
++ ifc_in32(&runtime->ifc_nand.col1);
++ ctrl->saved_rregs->ifc_nand.row2 =
++ ifc_in32(&runtime->ifc_nand.row2);
++ ctrl->saved_rregs->ifc_nand.col2 =
++ ifc_in32(&runtime->ifc_nand.col2);
++ ctrl->saved_rregs->ifc_nand.row3 =
++ ifc_in32(&runtime->ifc_nand.row3);
++ ctrl->saved_rregs->ifc_nand.col3 =
++ ifc_in32(&runtime->ifc_nand.col3);
++
++ ctrl->saved_rregs->ifc_nand.nand_fbcr =
++ ifc_in32(&runtime->ifc_nand.nand_fbcr);
++ ctrl->saved_rregs->ifc_nand.nand_fir0 =
++ ifc_in32(&runtime->ifc_nand.nand_fir0);
++ ctrl->saved_rregs->ifc_nand.nand_fir1 =
++ ifc_in32(&runtime->ifc_nand.nand_fir1);
++ ctrl->saved_rregs->ifc_nand.nand_fir2 =
++ ifc_in32(&runtime->ifc_nand.nand_fir2);
++ ctrl->saved_rregs->ifc_nand.nand_csel =
++ ifc_in32(&runtime->ifc_nand.nand_csel);
++ ctrl->saved_rregs->ifc_nand.nandseq_strt =
++ ifc_in32(
++ &runtime->ifc_nand.nandseq_strt);
++ ctrl->saved_rregs->ifc_nand.nand_evter_en =
++ ifc_in32(
++ &runtime->ifc_nand.nand_evter_en);
++ ctrl->saved_rregs->ifc_nand.nanndcr =
++ ifc_in32(&runtime->ifc_nand.nanndcr);
++ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
++ ifc_in32(
++ &runtime->ifc_nand.nand_dll_lowcfg0);
++ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
++ ifc_in32(
++ &runtime->ifc_nand.nand_dll_lowcfg1);
++
++ /* IFC controller NOR machine registers */
++ ctrl->saved_rregs->ifc_nor.nor_evter_en =
++ ifc_in32(
++ &runtime->ifc_nor.nor_evter_en);
++ ctrl->saved_rregs->ifc_nor.norcr =
++ ifc_in32(&runtime->ifc_nor.norcr);
++
++ /* IFC controller GPCM Machine registers */
++ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
++ ifc_in32(
++ &runtime->ifc_gpcm.gpcm_evter_en);
++ }
++
++/* save the interrupt values */
++ ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
++ ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
++ ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
++ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
++
++ return 0;
++}
++
++/* restore ifc registers */
++static int fsl_ifc_resume(struct device *dev)
++{
++ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
++ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
++ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
++ struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
++ struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
++ uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
++
++/*
++ * IFC interrupts disabled
++ */
++ ifc_out32(0x0, &fcm->cm_evter_intr_en);
++ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
++ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
++ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
++
++
++ if (ctrl->saved_gregs) {
++ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
++ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
++ &fcm->cspr_cs[ifc_bank].cspr_ext);
++ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
++ &fcm->cspr_cs[ifc_bank].cspr);
++ ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
++ &fcm->amask_cs[ifc_bank].amask);
++ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
++ &fcm->csor_cs[ifc_bank].csor_ext);
++ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
++ &fcm->csor_cs[ifc_bank].csor);
++ for (i = 0; i < 4; i++) {
++ ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
++ &fcm->ftim_cs[ifc_bank].ftim[i]);
++ }
++ }
++ ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
++ ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
++ ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
++ ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
++ ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
++ }
++
++ if (ctrl->saved_rregs) {
++ /* IFC controller NAND machine registers */
++ ifc_out32(savd_rregs->ifc_nand.ncfgr,
++ &runtime->ifc_nand.ncfgr);
++ ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
++ &runtime->ifc_nand.nand_fcr0);
++ ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
++ &runtime->ifc_nand.nand_fcr1);
++ ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
++ ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
++ ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
++ ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
++ ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
++ ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
++ ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
++ ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
++ ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
++ &runtime->ifc_nand.nand_fbcr);
++ ifc_out32(savd_rregs->ifc_nand.nand_fir0,
++ &runtime->ifc_nand.nand_fir0);
++ ifc_out32(savd_rregs->ifc_nand.nand_fir1,
++ &runtime->ifc_nand.nand_fir1);
++ ifc_out32(savd_rregs->ifc_nand.nand_fir2,
++ &runtime->ifc_nand.nand_fir2);
++ ifc_out32(savd_rregs->ifc_nand.nand_csel,
++ &runtime->ifc_nand.nand_csel);
++ ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
++ &runtime->ifc_nand.nandseq_strt);
++ ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
++ &runtime->ifc_nand.nand_evter_en);
++ ifc_out32(savd_rregs->ifc_nand.nanndcr,
++ &runtime->ifc_nand.nanndcr);
++ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
++ &runtime->ifc_nand.nand_dll_lowcfg0);
++ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
++ &runtime->ifc_nand.nand_dll_lowcfg1);
++
++ /* IFC controller NOR machine registers */
++ ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
++ &runtime->ifc_nor.nor_evter_en);
++ ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
++
++ /* IFC controller GPCM Machine registers */
++ ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
++ &runtime->ifc_gpcm.gpcm_evter_en);
++
++ /* IFC interrupts enabled */
++ ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
++ &fcm->cm_evter_intr_en);
++ ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
++ &runtime->ifc_nand.nand_evter_intr_en);
++ ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
++ &runtime->ifc_nor.nor_evter_intr_en);
++ ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
++ &runtime->ifc_gpcm.gpcm_evter_intr_en);
++
++ kfree(ctrl->saved_gregs);
++ kfree(ctrl->saved_rregs);
++ ctrl->saved_gregs = NULL;
++ ctrl->saved_rregs = NULL;
++ }
++
++ ver = ifc_in32(&fcm->ifc_rev);
++ ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
++ if (ver >= FSL_IFC_V1_3_0) {
++
++ ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
++ &runtime->ifc_nand.ncfgr);
++ /* wait for SRAM_INIT bit to be clear or timeout */
++ timeout = 10;
++ while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
++ IFC_NAND_SRAM_INIT_EN) && timeout) {
++ mdelay(IFC_TIMEOUT_MSECS);
++ timeout--;
++ }
++
++ if (!timeout)
++ dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
++ }
++
++ return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
+ static const struct of_device_id fsl_ifc_match[] = {
+ {
+ .compatible = "fsl,ifc",
+@@ -318,10 +576,15 @@ static const struct of_device_id fsl_ifc_match[] = {
+ {},
+ };
+
++static const struct dev_pm_ops ifc_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
++};
++
+ static struct platform_driver fsl_ifc_ctrl_driver = {
+ .driver = {
+ .name = "fsl-ifc",
+ .of_match_table = fsl_ifc_match,
++ .pm = &ifc_pm_ops,
+ },
+ .probe = fsl_ifc_ctrl_probe,
+ .remove = fsl_ifc_ctrl_remove,
+diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
+index 11d63046..38b90301 100644
+--- a/drivers/mtd/maps/physmap_of.c
++++ b/drivers/mtd/maps/physmap_of.c
+@@ -20,6 +20,7 @@
+ #include <linux/mtd/map.h>
+ #include <linux/mtd/partitions.h>
+ #include <linux/mtd/concat.h>
++#include <linux/mtd/cfi_endian.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+@@ -209,6 +210,9 @@ static int of_flash_probe(struct platform_device *dev)
+ return err;
+ }
+
++ if (of_property_read_bool(dp->parent, "big-endian"))
++ info->list[i].map.swap = CFI_BIG_ENDIAN;
++
+ err = -ENOMEM;
+ info->list[i].map.virt = ioremap(info->list[i].map.phys,
+ info->list[i].map.size);
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index b254090b..961f1aa1 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC
+
+ config MTD_NAND_FSL_IFC
+ tristate "NAND support for Freescale IFC controller"
+- depends on FSL_SOC || ARCH_LAYERSCAPE
++ depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
+ select FSL_IFC
+ select MEMORY
+ help
+diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
+index d1570f51..785e9ee0 100644
+--- a/drivers/mtd/nand/fsl_ifc_nand.c
++++ b/drivers/mtd/nand/fsl_ifc_nand.c
+@@ -904,9 +904,12 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
+ chip->ecc.algo = NAND_ECC_HAMMING;
+ }
+
+- if (ctrl->version == FSL_IFC_VERSION_1_1_0)
++ if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
+ fsl_ifc_sram_init(priv);
+
++ if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
++ priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
++
+ return 0;
+ }
+
+diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
+index c332f0a4..a41d21b6 100644
+--- a/include/linux/fsl_ifc.h
++++ b/include/linux/fsl_ifc.h
+@@ -274,6 +274,8 @@
+ */
+ /* Auto Boot Mode */
+ #define IFC_NAND_NCFGR_BOOT 0x80000000
++/* SRAM INIT EN */
++#define IFC_NAND_SRAM_INIT_EN 0x20000000
+ /* Addressing Mode-ROW0+n/COL0 */
+ #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
+ /* Addressing Mode-ROW0+n/COL0+n */
+@@ -861,6 +863,11 @@ struct fsl_ifc_ctrl {
+ u32 nand_stat;
+ wait_queue_head_t nand_wait;
+ bool little_endian;
++#ifdef CONFIG_PM_SLEEP
++ /*save regs when system goes to deep sleep*/
++ struct fsl_ifc_global *saved_gregs;
++ struct fsl_ifc_runtime *saved_rregs;
++#endif
+ };
+
+ extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+--
+2.14.1
+