layerscape: drop linux 4.4 support

This patch is to drop linux 4.4 for layerscape.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>

1 files changed, 0 insertions, 790 deletions

diff --git a/target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch b/target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch
deleted file mode 100644
index c8aaeee2c8..0000000000
--- a/target/linux/layerscape/patches-4.4/3135-arm64-Add-DTS-support-for-FSL-s-LS1088ARDB.patch
+++ /dev/null
@@ -1,790 +0,0 @@
-From cbacf87fa6fb262c98033405f15697798c3a9c5d Mon Sep 17 00:00:00 2001
-From: Zhao Qiang <qiang.zhao@nxp.com>
-Date: Sun, 9 Oct 2016 14:31:50 +0800
-Subject: [PATCH 135/141] arm64: Add DTS support for FSL's LS1088ARDB
-
-Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
----
- arch/arm64/boot/dts/freescale/Makefile            |    1 +
- arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts |  203 ++++++++
- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi    |  557 +++++++++++++++++++++
- 3 files changed, 761 insertions(+)
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-
---- a/arch/arm64/boot/dts/freescale/Makefile
-+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
-  
- always		:= $(dtb-y)
- subdir-y	:= $(dts-dirs)
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
-@@ -0,0 +1,203 @@
-+/*
-+ * Device Tree file for Freescale LS1088a RDB board
-+ *
-+ * Copyright (C) 2015, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2.  This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+/dts-v1/;
-+
-+#include "fsl-ls1088a.dtsi"
-+
-+/ {
-+	model = "Freescale Layerscape 1088a RDB Board";
-+	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
-+};
-+
-+&esdhc {
-+	status = "okay";
-+};
-+
-+&ifc {
-+	status = "disabled";
-+};
-+
-+&ftm0 {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+	pca9547@77 {
-+		compatible = "philips,pca9547";
-+		reg = <0x77>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		i2c@2 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x2>;
-+
-+			ina220@40 {
-+				compatible = "ti,ina220";
-+				reg = <0x40>;
-+				shunt-resistor = <1000>;
-+			};
-+		};
-+
-+		i2c@3 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x3>;
-+
-+			rtc@51 {
-+				compatible = "nxp,pcf2129";
-+				reg = <0x51>;
-+				/* IRQ10_B */
-+				interrupts = <0 150 0x4>;
-+			};
-+
-+			adt7461a@4c {
-+				compatible = "adt7461a";
-+				reg = <0x4c>;
-+			};
-+		};
-+	};
-+};
-+
-+&i2c1 {
-+	status = "disabled";
-+};
-+
-+&i2c2 {
-+	status = "disabled";
-+};
-+
-+&i2c3 {
-+	status = "disabled";
-+};
-+
-+&dspi {
-+	status = "disabled";
-+};
-+
-+&qspi {
-+	status = "okay";
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+
-+	qflash1: s25fs512s@1 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <1>;
-+	};
-+};
-+
-+&sata0 {
-+	status = "okay";
-+};
-+
-+&usb0 {
-+	status = "okay";
-+};
-+
-+&usb1 {
-+	status = "okay";
-+};
-+
-+&serial0 {
-+	status = "okay";
-+};
-+
-+&serial1 {
-+	status = "okay";
-+};
-+
-+&emdio1 {
-+	/* Freescale F104 PHY1 */
-+	mdio1_phy1: emdio1_phy@1 {
-+		reg = <0x1c>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy2: emdio1_phy@2 {
-+		reg = <0x1d>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy3: emdio1_phy@3 {
-+		reg = <0x1e>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy4: emdio1_phy@4 {
-+		reg = <0x1f>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	/* F104 PHY2 */
-+	mdio1_phy5: emdio1_phy@5 {
-+		reg = <0x0c>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy6: emdio1_phy@6 {
-+		reg = <0x0d>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy7: emdio1_phy@7 {
-+		reg = <0x0e>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy8: emdio1_phy@8 {
-+		reg = <0x0f>;
-+		phy-connection-type = "qsgmii";
-+	};
-+};
-+
-+&emdio2 {
-+	/* Aquantia AQR105 10G PHY */
-+	mdio2_phy1: emdio2_phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+/* DPMAC connections to external PHYs
-+ * based on LS1088A RM RevC - $24.1.2 SerDes Options
-+ */
-+/* DPMAC1 is 10G SFP+, fixed link */
-+&dpmac2 {
-+	phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac3 {
-+	phy-handle = <&mdio1_phy5>;
-+};
-+&dpmac4 {
-+	phy-handle = <&mdio1_phy6>;
-+};
-+&dpmac5 {
-+	phy-handle = <&mdio1_phy7>;
-+};
-+&dpmac6 {
-+	phy-handle = <&mdio1_phy8>;
-+};
-+&dpmac7 {
-+	phy-handle = <&mdio1_phy1>;
-+};
-+&dpmac8 {
-+	phy-handle = <&mdio1_phy2>;
-+};
-+&dpmac9 {
-+	phy-handle = <&mdio1_phy3>;
-+};
-+&dpmac10 {
-+	phy-handle = <&mdio1_phy4>;
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-@@ -0,0 +1,557 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1088A family SoC.
-+ *
-+ * Copyright (C) 2015, Freescale Semiconductor
-+ *
-+ */
-+
-+/memreserve/ 0x80000000 0x00010000;
-+
-+/ {
-+	compatible = "fsl,ls1088a";
-+	interrupt-parent = <&gic>;
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	cpus {
-+		#address-cells = <2>;
-+		#size-cells = <0>;
-+
-+		/* We have 2 clusters having 4 Cortex-A57 cores each */
-+		cpu0: cpu@0 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x0>;
-+			clocks = <&clockgen 1 0>;
-+		};
-+
-+		cpu1: cpu@1 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x1>;
-+			clocks = <&clockgen 1 0>;
-+		};
-+
-+		cpu2: cpu@2 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x2>;
-+			clocks = <&clockgen 1 0>;
-+		};
-+
-+		cpu3: cpu@3 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x3>;
-+			clocks = <&clockgen 1 0>;
-+		};
-+
-+		cpu4: cpu@100 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x100>;
-+			clocks = <&clockgen 1 1>;
-+		};
-+
-+		cpu5: cpu@101 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x101>;
-+			clocks = <&clockgen 1 1>;
-+		};
-+
-+		cpu6: cpu@102 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x102>;
-+			clocks = <&clockgen 1 1>;
-+		};
-+
-+		cpu7: cpu@103 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0 0x103>;
-+			clocks = <&clockgen 1 1>;
-+		};
-+	};
-+
-+	pmu {
-+		compatible = "arm,armv8-pmuv3";
-+		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
-+	};
-+
-+	gic: interrupt-controller@6000000 {
-+		compatible = "arm,gic-v3";
-+		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
-+		      <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
-+		      <0x0 0x0c0c0000 0 0x2000>, /* GICC */
-+		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
-+		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
-+		#interrupt-cells = <3>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		interrupt-controller;
-+		interrupts = <1 9 0x4>;
-+
-+		its: gic-its@6020000 {
-+			compatible = "arm,gic-v3-its";
-+			msi-controller;
-+			reg = <0x0 0x6020000 0 0x20000>;
-+		};
-+	};
-+
-+	sysclk: sysclk {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <100000000>;
-+		clock-output-names = "sysclk";
-+	};
-+
-+	clockgen: clocking@1300000 {
-+		compatible = "fsl,ls2080a-clockgen", "fsl,ls1088a-clockgen";
-+		reg = <0 0x1300000 0 0xa0000>;
-+		#clock-cells = <2>;
-+		clocks = <&sysclk>;
-+	};
-+
-+	serial0: serial@21c0500 {
-+		device_type = "serial";
-+		compatible = "fsl,ns16550", "ns16550a";
-+		reg = <0x0 0x21c0500 0x0 0x100>;
-+		clocks = <&clockgen 4 3>;
-+		interrupts = <0 32 0x4>; /* Level high type */
-+	};
-+
-+	serial1: serial@21c0600 {
-+		device_type = "serial";
-+		compatible = "fsl,ns16550", "ns16550a";
-+		reg = <0x0 0x21c0600 0x0 0x100>;
-+		clocks = <&clockgen 4 3>;
-+		interrupts = <0 32 0x4>; /* Level high type */
-+	};
-+
-+	gpio0: gpio@2300000 {
-+		compatible = "fsl,qoriq-gpio";
-+		reg = <0x0 0x2300000 0x0 0x10000>;
-+		interrupts = <0 36 0x4>; /* Level high type */
-+		gpio-controller;
-+		little-endian;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+	};
-+
-+	gpio1: gpio@2310000 {
-+		compatible = "fsl,qoriq-gpio";
-+		reg = <0x0 0x2310000 0x0 0x10000>;
-+		interrupts = <0 36 0x4>; /* Level high type */
-+		gpio-controller;
-+		little-endian;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+	};
-+
-+	gpio2: gpio@2320000 {
-+		compatible = "fsl,qoriq-gpio";
-+		reg = <0x0 0x2320000 0x0 0x10000>;
-+		interrupts = <0 37 0x4>; /* Level high type */
-+		gpio-controller;
-+		little-endian;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+	};
-+
-+	gpio3: gpio@2330000 {
-+		compatible = "fsl,qoriq-gpio";
-+		reg = <0x0 0x2330000 0x0 0x10000>;
-+		interrupts = <0 37 0x4>; /* Level high type */
-+		gpio-controller;
-+		little-endian;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+	};
-+
-+	/* TODO: WRIOP (CCSR?) */
-+	emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
-+		compatible = "fsl,fman-memac-mdio";
-+		reg = <0x0 0x8B96000 0x0 0x1000>;
-+		device_type = "mdio";
-+		little-endian;	/* force the driver in LE mode */
-+
-+		/* Not necessary on the QDS, but needed on the RDB */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+	};
-+
-+	emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
-+		compatible = "fsl,fman-memac-mdio";
-+		reg = <0x0 0x8B97000 0x0 0x1000>;
-+		device_type = "mdio";
-+		little-endian;	/* force the driver in LE mode */
-+
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+	};
-+
-+	ifc: ifc@2240000 {
-+		compatible = "fsl,ifc", "simple-bus";
-+		reg = <0x0 0x2240000 0x0 0x20000>;
-+		interrupts = <0 21 0x4>; /* Level high type */
-+		little-endian;
-+		#address-cells = <2>;
-+		#size-cells = <1>;
-+
-+		ranges = <0 0 0x5 0x80000000 0x08000000
-+			  2 0 0x5 0x30000000 0x00010000
-+			  3 0 0x5 0x20000000 0x00010000>;
-+	};
-+
-+	esdhc: esdhc@2140000 {
-+		compatible = "fsl,ls2080a-esdhc", "fsl,ls1088a-esdhc", "fsl,esdhc";
-+		reg = <0x0 0x2140000 0x0 0x10000>;
-+		interrupts = <0 28 0x4>; /* Level high type */
-+		clock-frequency = <0>;
-+		voltage-ranges = <1800 1800 3300 3300>;
-+		sdhci,auto-cmd12;
-+		little-endian;
-+		bus-width = <4>;
-+	};
-+
-+	ftm0: ftm0@2800000 {
-+		compatible = "fsl,ftm-alarm";
-+		reg = <0x0 0x2800000 0x0 0x10000>;
-+		interrupts = <0 44 4>;
-+	};
-+
-+	reset: reset@1E60000 {
-+		compatible = "fsl,ls-reset";
-+		reg = <0x0 0x1E60000 0x0 0x10000>;
-+	};
-+
-+	dspi: dspi@2100000 {
-+		compatible = "fsl,ls2085a-dspi", "fsl,ls1088a-dspi";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0 0x2100000 0x0 0x10000>;
-+		interrupts = <0 26 0x4>; /* Level high type */
-+		clocks = <&clockgen 4 3>;
-+		clock-names = "dspi";
-+		spi-num-chipselects = <5>;
-+		bus-num = <0>;
-+	};
-+
-+	i2c0: i2c@2000000 {
-+		compatible = "fsl,vf610-i2c";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0 0x2000000 0x0 0x10000>;
-+		interrupts = <0 34 0x4>; /* Level high type */
-+		clock-names = "i2c";
-+		clocks = <&clockgen 4 3>;
-+	};
-+
-+	i2c1: i2c@2010000 {
-+		compatible = "fsl,vf610-i2c";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0 0x2010000 0x0 0x10000>;
-+		interrupts = <0 34 0x4>; /* Level high type */
-+		clock-names = "i2c";
-+		clocks = <&clockgen 4 3>;
-+	};
-+
-+	i2c2: i2c@2020000 {
-+		compatible = "fsl,vf610-i2c";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0 0x2020000 0x0 0x10000>;
-+		interrupts = <0 35 0x4>; /* Level high type */
-+		clock-names = "i2c";
-+		clocks = <&clockgen 4 3>;
-+	};
-+
-+	i2c3: i2c@2030000 {
-+		compatible = "fsl,vf610-i2c";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0 0x2030000 0x0 0x10000>;
-+		interrupts = <0 35 0x4>; /* Level high type */
-+		clock-names = "i2c";
-+		clocks = <&clockgen 4 3>;
-+	};
-+
-+	qspi: quadspi@20c0000 {
-+		compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0 0x20c0000 0x0 0x10000>,
-+		      <0x0 0x20000000 0x0 0x10000000>;
-+		reg-names = "QuadSPI", "QuadSPI-memory";
-+		interrupts = <0 25 0x4>; /* Level high type */
-+		clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+		clock-names = "qspi_en", "qspi";
-+	};
-+
-+	pcie@3400000 {
-+		compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-+		       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
-+		reg-names = "regs", "config";
-+		interrupts = <0 108 0x4>; /* aer interrupt */
-+		interrupt-names = "aer";
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		device_type = "pci";
-+		dma-coherent;
-+		num-lanes = <4>;
-+		bus-range = <0x0 0xff>;
-+		ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
-+			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+		msi-parent = <&its>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
-+				<0000 0 0 2 &gic 0 0 0 110 4>,
-+				<0000 0 0 3 &gic 0 0 0 111 4>,
-+				<0000 0 0 4 &gic 0 0 0 112 4>;
-+	};
-+	pcie@3500000 {
-+		compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+		reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
-+		       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
-+		reg-names = "regs", "config";
-+		interrupts = <0 113 0x4>; /* aer interrupt */
-+		interrupt-names = "aer";
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		device_type = "pci";
-+		dma-coherent;
-+		num-lanes = <4>;
-+		bus-range = <0x0 0xff>;
-+		ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
-+			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+		msi-parent = <&its>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
-+				<0000 0 0 2 &gic 0 0 0 115 4>,
-+				<0000 0 0 3 &gic 0 0 0 116 4>,
-+				<0000 0 0 4 &gic 0 0 0 117 4>;
-+	};
-+
-+	pcie@3600000 {
-+		compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+		reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
-+		       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
-+		reg-names = "regs", "config";
-+		interrupts = <0 118 0x4>; /* aer interrupt */
-+		interrupt-names = "aer";
-+		#address-cells = <3>;
-+		#size-cells = <2>;
-+		device_type = "pci";
-+		dma-coherent;
-+		num-lanes = <8>;
-+		bus-range = <0x0 0xff>;
-+		ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
-+			  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+		msi-parent = <&its>;
-+		#interrupt-cells = <1>;
-+		interrupt-map-mask = <0 0 0 7>;
-+		interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
-+				<0000 0 0 2 &gic 0 0 0 120 4>,
-+				<0000 0 0 3 &gic 0 0 0 121 4>,
-+				<0000 0 0 4 &gic 0 0 0 122 4>;
-+	};
-+
-+	sata0: sata@3200000 {
-+		compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
-+		reg = <0x0 0x3200000 0x0 0x10000>;
-+		interrupts = <0 133 0x4>; /* Level high type */
-+		clocks = <&clockgen 4 3>;
-+	};
-+
-+	usb0: usb3@3100000 {
-+		compatible = "snps,dwc3";
-+		reg = <0x0 0x3100000 0x0 0x10000>;
-+		interrupts = <0 80 0x4>; /* Level high type */
-+		dr_mode = "host";
-+		configure-gfladj;
-+		snps,dis_rxdet_inp3_quirk;
-+	};
-+
-+	usb1: usb3@3110000 {
-+		compatible = "snps,dwc3";
-+		reg = <0x0 0x3110000 0x0 0x10000>;
-+		interrupts = <0 81 0x4>; /* Level high type */
-+		dr_mode = "host";
-+		configure-gfladj;
-+		snps,dis_rxdet_inp3_quirk;
-+	};
-+
-+	smmu: iommu@5000000 {
-+		compatible = "arm,mmu-500";
-+		reg = <0 0x5000000 0 0x800000>;
-+		#global-interrupts = <12>;
-+		interrupts = <0 13 4>, /* global secure fault */
-+			     <0 14 4>, /* combined secure interrupt */
-+			     <0 15 4>, /* global non-secure fault */
-+			     <0 16 4>, /* combined non-secure interrupt */
-+			/* performance counter interrupts 0-7 */
-+			     <0 211 4>,
-+			     <0 212 4>,
-+			     <0 213 4>,
-+			     <0 214 4>,
-+			     <0 215 4>,
-+			     <0 216 4>,
-+			     <0 217 4>,
-+			     <0 218 4>,
-+			/* per context interrupt, 64 interrupts */
-+			     <0 146 4>,
-+			     <0 147 4>,
-+			     <0 148 4>,
-+			     <0 149 4>,
-+			     <0 150 4>,
-+			     <0 151 4>,
-+			     <0 152 4>,
-+			     <0 153 4>,
-+			     <0 154 4>,
-+			     <0 155 4>,
-+			     <0 156 4>,
-+			     <0 157 4>,
-+			     <0 158 4>,
-+			     <0 159 4>,
-+			     <0 160 4>,
-+			     <0 161 4>,
-+			     <0 162 4>,
-+			     <0 163 4>,
-+			     <0 164 4>,
-+			     <0 165 4>,
-+			     <0 166 4>,
-+			     <0 167 4>,
-+			     <0 168 4>,
-+			     <0 169 4>,
-+			     <0 170 4>,
-+			     <0 171 4>,
-+			     <0 172 4>,
-+			     <0 173 4>,
-+			     <0 174 4>,
-+			     <0 175 4>,
-+			     <0 176 4>,
-+			     <0 177 4>,
-+			     <0 178 4>,
-+			     <0 179 4>,
-+			     <0 180 4>,
-+			     <0 181 4>,
-+			     <0 182 4>,
-+			     <0 183 4>,
-+			     <0 184 4>,
-+			     <0 185 4>,
-+			     <0 186 4>,
-+			     <0 187 4>,
-+			     <0 188 4>,
-+			     <0 189 4>,
-+			     <0 190 4>,
-+			     <0 191 4>,
-+			     <0 192 4>,
-+			     <0 193 4>,
-+			     <0 194 4>,
-+			     <0 195 4>,
-+			     <0 196 4>,
-+			     <0 197 4>,
-+			     <0 198 4>,
-+			     <0 199 4>,
-+			     <0 200 4>,
-+			     <0 201 4>,
-+			     <0 202 4>,
-+			     <0 203 4>,
-+			     <0 204 4>,
-+			     <0 205 4>,
-+			     <0 206 4>,
-+			     <0 207 4>,
-+			     <0 208 4>,
-+			     <0 209 4>;
-+		mmu-masters = <&fsl_mc 0x300 0>;
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupts = <1 13 0x1>,/*Phy Secure PPI, edge triggered*/
-+			     <1 14 0x1>, /*Phy Non-Secure PPI, edge triggered*/
-+			     <1 11 0x1>, /*Virtual PPI, edge triggered */
-+			     <1 10 0x1>; /*Hypervisor PPI, edge triggered */
-+	};
-+
-+	fsl_mc: fsl-mc@80c000000 {
-+		compatible = "fsl,qoriq-mc";
-+		#stream-id-cells = <2>;
-+		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
-+		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-+		msi-parent = <&its>;
-+		#address-cells = <3>;
-+		#size-cells = <1>;
-+
-+		/*
-+		 * Region type 0x0 - MC portals
-+		 * Region type 0x1 - QBMAN portals
-+		 */
-+		ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
-+			  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
-+
-+		dpmacs {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			dpmac1: dpmac@1 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <1>;
-+			};
-+			dpmac2: dpmac@2 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <2>;
-+			};
-+			dpmac3: dpmac@3 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <3>;
-+			};
-+			dpmac4: dpmac@4 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <4>;
-+			};
-+			dpmac5: dpmac@5 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <5>;
-+			};
-+			dpmac6: dpmac@6 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <6>;
-+			};
-+			dpmac7: dpmac@7 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <7>;
-+			};
-+			dpmac8: dpmac@8 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <8>;
-+			};
-+			dpmac9: dpmac@9 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <9>;
-+			};
-+			dpmac10: dpmac@10 {
-+				compatible = "fsl,qoriq-mc-dpmac";
-+				reg = <0xa>;
-+			};
-+		};
-+	};
-+
-+
-+	memory@80000000 {
-+		device_type = "memory";
-+		reg = <0x00000000 0x80000000 0 0x80000000>;
-+		      /* DRAM space 1 - 2 GB DRAM */
-+	};
-+};