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| author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:14:32 +0800 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
| commit | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (patch) | |
| tree | d92c7296f82d46d1b2da30933a97595f6cb8ad66 /target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch | |
| parent | a34f96d6cf80c7c3c425076714d9c4caa67e3670 (diff) | |
| download | upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.gz upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.tar.bz2 upstream-c6c731fe311f7da42777ffd31804a4f6aa3f8e19.zip | |
layerscape: add 64b/32b target for ls1043ardb device
Add support for NXP layerscape ls1043ardb 64b/32b Dev board.
LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.
64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.
All of 4.4 kernel patches porting from SDK release or upstream.
QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch b/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch new file mode 100644 index 0000000000..f48150dab2 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch @@ -0,0 +1,34 @@ +From 481b1bc4ce0d58107887558342e50d6323a9601d Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang <jszhang@marvell.com> +Date: Thu, 7 Jan 2016 14:12:38 +0800 +Subject: [PATCH 54/70] PCI: designware: Explain why we don't program ATU for + some platforms + +Some platforms don't support ATU, e.g., pci-keystone.c. These platforms +use their own address translation component rather than ATU, and they +provide the rd_other_conf and wr_other_conf methods to program the +translation component and perform the access. + +Add a comment to explain why we don't program the ATU for these platforms. + +[bhelgaas: changelog] +Signed-off-by: Jisheng Zhang <jszhang@marvell.com> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +--- + drivers/pci/host/pcie-designware.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -517,6 +517,11 @@ int dw_pcie_host_init(struct pcie_port * + if (pp->ops->host_init) + pp->ops->host_init(pp); + ++ /* ++ * If the platform provides ->rd_other_conf, it means the platform ++ * uses its own address translation component rather than ATU, so ++ * we should not program the ATU here. ++ */ + if (!pp->ops->rd_other_conf) + dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_MEM, pp->mem_base, |