layerscape: upgrade kernel to 4.14

This patch is to upgrade kernel to 4.14 for layerscape.
patches-4.14 for layerscape included two categories.

- NXP Layerscape SDK kernel-4.14 patches

  All patches on tag LSDK-18.09-V4.14 were ported to OpenWrt
  kernel. Since there were hundreds patches, we had to make
  an all-in-one patch for each IP/feature.
  See below links for LSDK kernel.
  https://lsdk.github.io/components.html
  https://source.codeaurora.org/external/qoriq/qoriq-components/linux

- Non-LSDK kernel patches

  Other patches which were not in LSDK were just put in patches-4.14.
  Kept below patches from patches-4.9.
  303-dts-layerscape-add-traverse-ls1043.patch
  821-add-esdhc-vsel-to-ls1043.patch
  822-rgmii-fixed-link.patch

  Renamed and rebase them as below in patches-4.14,
  303-add-DTS-for-Traverse-LS1043-Boards.patch
  712-sdk-dpaa-rgmii-fixed-link.patch
  824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>

1 files changed, 37 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch b/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
new file mode 100644
index 0000000000..dcd1535601
--- /dev/null
+++ b/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
@@ -0,0 +1,37 @@
+From d94f8863307c0f7fb7aeb2084cc666c47991d78b Mon Sep 17 00:00:00 2001
+From: Biwen Li <biwen.li@nxp.com>
+Date: Mon, 19 Nov 2018 10:26:57 +0800
+Subject: [PATCH] clock: support layerscape
+This is an integrated patch of clock for layerscape
+
+Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
+Signed-off-by: Biwen Li <biwen.li@nxp.com>
+---
+ drivers/clk/clk-qoriq.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -41,7 +41,7 @@ struct clockgen_pll_div {
+ };
+ 
+ struct clockgen_pll {
+-	struct clockgen_pll_div div[4];
++	struct clockgen_pll_div div[8];
+ };
+ 
+ #define CLKSEL_VALID	1
+@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct
+ 		struct clk *clk;
+ 		int ret;
+ 
++		/*
++		 * For platform PLL, there are 8 divider clocks.
++		 * For core PLL, there are 4 divider clocks at most.
++		 */
++		if (idx != 0 && i >= 4)
++			break;
++
+ 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
+ 			 "cg-pll%d-div%d", idx, i + 1);
+