adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support.

SVN-Revision: 24526

1 files changed, 436 insertions, 0 deletions

diff --git a/target/linux/lantiq/patches/260-pci.patch b/target/linux/lantiq/patches/260-pci.patch
new file mode 100644
index 0000000000..d086b25e8b
--- /dev/null
+++ b/target/linux/lantiq/patches/260-pci.patch
@@ -0,0 +1,436 @@
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capc
+ obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o
+ obj-$(CONFIG_MIKROTIK_RB532)	+= pci-rc32434.o ops-rc32434.o fixup-rc32434.o
+ obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= pci-octeon.o pcie-octeon.o
++obj-$(CONFIG_LANTIQ)			+= pci-lantiq.o ops-lantiq.o
+ 
+ ifdef CONFIG_PCI_MSI
+ obj-$(CONFIG_CPU_CAVIUM_OCTEON)	+= msi-octeon.o
+--- /dev/null
++++ b/arch/mips/pci/ops-lantiq.c
+@@ -0,0 +1,127 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mm.h>
++#include <asm/addrspace.h>
++#include <linux/vmalloc.h>
++
++#include <xway.h>
++
++#define LQ_PCI_CFG_BUSNUM_SHF 16
++#define LQ_PCI_CFG_DEVNUM_SHF 11
++#define LQ_PCI_CFG_FUNNUM_SHF 8
++
++#define PCI_ACCESS_READ  0
++#define PCI_ACCESS_WRITE 1
++
++extern u32 lq_pci_mapped_cfg;
++
++static int
++lq_pci_config_access(unsigned char access_type,
++		struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
++{
++	unsigned long cfg_base;
++	unsigned long flags;
++
++	u32 temp;
++
++	/* we support slot from 0 to 15 */
++	/* dev_fn 0&0x68 (AD29) is ifxmips itself */
++	if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
++			|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
++		return 1;
++
++	spin_lock_irqsave(&ebu_lock, flags);
++
++	cfg_base = lq_pci_mapped_cfg;
++	cfg_base |= (bus->number << LQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
++			LQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
++
++	/* Perform access */
++	if (access_type == PCI_ACCESS_WRITE)
++	{
++#ifdef CONFIG_SWAP_IO_SPACE
++		lq_w32(swab32(*data), ((u32*)cfg_base));
++#else
++		lq_w32(*data, ((u32*)cfg_base));
++#endif
++	} else {
++		*data = lq_r32(((u32*)(cfg_base)));
++#ifdef CONFIG_SWAP_IO_SPACE
++		*data = swab32(*data);
++#endif
++	}
++	wmb();
++
++	/* clean possible Master abort */
++	cfg_base = (lq_pci_mapped_cfg | (0x0 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
++	temp = lq_r32(((u32*)(cfg_base)));
++#ifdef CONFIG_SWAP_IO_SPACE
++	temp = swab32 (temp);
++#endif
++	cfg_base = (lq_pci_mapped_cfg | (0x68 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
++	lq_w32(temp, ((u32*)cfg_base));
++
++	spin_unlock_irqrestore(&ebu_lock, flags);
++
++	if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
++		return 1;
++
++	return 0;
++}
++
++int
++lq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
++		int where, int size, u32 * val)
++{
++	u32 data = 0;
++
++	if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	if (size == 1)
++		*val = (data >> ((where & 3) << 3)) & 0xff;
++	else if (size == 2)
++		*val = (data >> ((where & 3) << 3)) & 0xffff;
++	else
++		*val = data;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++int
++lq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
++		int where, int size, u32 val)
++{
++	u32 data = 0;
++
++	if (size == 4)
++	{
++		data = val;
++	} else {
++		if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
++			return PCIBIOS_DEVICE_NOT_FOUND;
++
++		if (size == 1)
++			data = (data & ~(0xff << ((where & 3) << 3))) |
++				(val << ((where & 3) << 3));
++		else if (size == 2)
++			data = (data & ~(0xffff << ((where & 3) << 3))) |
++				(val << ((where & 3) << 3));
++	}
++
++	if (lq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	return PCIBIOS_SUCCESSFUL;
++}
+--- /dev/null
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -0,0 +1,293 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mm.h>
++#include <linux/vmalloc.h>
++#include <linux/platform_device.h>
++
++#include <asm/gpio.h>
++#include <asm/addrspace.h>
++
++#include <xway.h>
++#include <xway_irq.h>
++#include <lantiq_platform.h>
++
++#define LQ_PCI_CFG_BASE		0x17000000
++#define LQ_PCI_CFG_SIZE		0x00008000
++#define LQ_PCI_MEM_BASE		0x18000000
++#define LQ_PCI_MEM_SIZE		0x02000000
++#define LQ_PCI_IO_BASE		0x1AE00000
++#define LQ_PCI_IO_SIZE		0x00200000
++
++#define PCI_CR_FCI_ADDR_MAP0		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
++#define PCI_CR_FCI_ADDR_MAP1		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
++#define PCI_CR_FCI_ADDR_MAP2		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
++#define PCI_CR_FCI_ADDR_MAP3		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
++#define PCI_CR_FCI_ADDR_MAP4		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
++#define PCI_CR_FCI_ADDR_MAP5		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
++#define PCI_CR_FCI_ADDR_MAP6		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
++#define PCI_CR_FCI_ADDR_MAP7		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
++#define PCI_CR_CLK_CTRL			((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
++#define PCI_CR_PCI_MOD			((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
++#define PCI_CR_PC_ARB			((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
++#define PCI_CR_FCI_ADDR_MAP11hg		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
++#define PCI_CR_BAR11MASK		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
++#define PCI_CR_BAR12MASK		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
++#define PCI_CR_BAR13MASK		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
++#define PCI_CS_BASE_ADDR1		((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
++#define PCI_CR_PCI_ADDR_MAP11		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
++#define PCI_CR_FCI_BURST_LENGTH		((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
++#define PCI_CR_PCI_EOI			((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
++
++
++#define PCI_CS_STS_CMD			((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
++
++#define PCI_MASTER0_REQ_MASK_2BITS	8
++#define PCI_MASTER1_REQ_MASK_2BITS	10
++#define PCI_MASTER2_REQ_MASK_2BITS	12
++#define INTERNAL_ARB_ENABLE_BIT		0
++
++#define LQ_CGU_IFCCR		((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
++#define LQ_CGU_PCICR		((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
++
++extern int lq_pci_read_config_dword(struct pci_bus *bus,
++	unsigned int devfn, int where, int size, u32 *val);
++extern int lq_pci_write_config_dword(struct pci_bus *bus,
++	unsigned int devfn, int where, int size, u32 val);
++
++u32 lq_pci_mapped_cfg;
++
++/* Since the PCI REQ pins can be reused for other functionality, make it possible
++   to exclude those from interpretation by the PCI controller */
++static int lq_pci_req_mask = 0xf;
++
++struct pci_ops lq_pci_ops =
++{
++	.read = lq_pci_read_config_dword,
++	.write = lq_pci_write_config_dword
++};
++
++static struct resource pci_io_resource =
++{
++	.name = "pci io space",
++	.start = LQ_PCI_IO_BASE,
++	.end = LQ_PCI_IO_BASE + LQ_PCI_IO_SIZE - 1,
++	.flags = IORESOURCE_IO
++};
++
++static struct resource pci_mem_resource =
++{
++	.name = "pci memory space",
++	.start = LQ_PCI_MEM_BASE,
++	.end = LQ_PCI_MEM_BASE + LQ_PCI_MEM_SIZE - 1,
++	.flags = IORESOURCE_MEM
++};
++
++static struct pci_controller lq_pci_controller =
++{
++	.pci_ops = &lq_pci_ops,
++	.mem_resource = &pci_mem_resource,
++	.mem_offset	= 0x00000000UL,
++	.io_resource = &pci_io_resource,
++	.io_offset	= 0x00000000UL,
++};
++
++int
++pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	u8 pin;
++
++	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
++	switch(pin)
++	{
++		case 0:
++			break;
++		case 1:
++			//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
++			lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
++			lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
++			break;
++		case 2:
++		case 3:
++		case 4:
++			printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
++		default:
++			printk ("WARNING: invalid interrupt pin %d\n", pin);
++			return 1;
++	}
++	return 0;
++}
++
++static u32
++lq_calc_bar11mask(void)
++{
++	u32 mem, bar11mask;
++
++	/* BAR11MASK value depends on available memory on system. */
++	mem = num_physpages * PAGE_SIZE;
++	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8;
++
++	return bar11mask;
++}
++
++static void
++lq_pci_setup_clk(int external_clock)
++{
++	/* set clock to 33Mhz */
++	lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR);
++	lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000,	LQ_CGU_IFCCR);
++	if (external_clock)
++	{
++		lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR);
++		lq_w32((1 << 30), LQ_CGU_PCICR);
++	} else {
++		lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR);
++		lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR);
++	}
++}
++
++static void
++lq_pci_setup_gpio(void)
++{
++	/* PCI reset line is gpio driven */
++	lq_gpio_request(21, 0, 0, 1, "pci-reset");
++
++	/* PCI_REQ line */
++	lq_gpio_request(29, 1, 0, 0, "pci-req");
++
++	/* PCI_GNT line */
++	lq_gpio_request(30, 1, 0, 1, "pci-gnt");
++}
++
++static int __init
++lq_pci_startup(void)
++{
++	u32 temp_buffer;
++
++	/* setup pci clock and gpis used by pci */
++	lq_pci_setup_gpio();
++
++	/* enable auto-switching between PCI and EBU */
++	lq_w32(0xa, PCI_CR_CLK_CTRL);
++
++	/* busy, i.e. configuration is not done, PCI access has to be retried */
++	lq_w32(lq_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
++	wmb ();
++	/* BUS Master/IO/MEM access */
++	lq_w32(lq_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
++
++	/* enable external 2 PCI masters */
++	temp_buffer = lq_r32(PCI_CR_PC_ARB);
++	temp_buffer &= (~(lq_pci_req_mask << 16));
++	/* enable internal arbiter */
++	temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
++	/* enable internal PCI master reqest */
++	temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
++
++	/* enable EBU request */
++	temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
++
++	/* enable all external masters request */
++	temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
++	lq_w32(temp_buffer, PCI_CR_PC_ARB);
++	wmb ();
++
++	/* setup BAR memory regions */
++	lq_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
++	lq_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
++	lq_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
++	lq_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
++	lq_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
++	lq_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
++	lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
++	lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
++	lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
++	lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK);
++	lq_w32(0, PCI_CR_PCI_ADDR_MAP11);
++	lq_w32(0, PCI_CS_BASE_ADDR1);
++#ifdef CONFIG_SWAP_IO_SPACE
++	/* both TX and RX endian swap are enabled */
++	lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
++	wmb ();
++#endif
++	/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
++	lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
++	lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
++	/*use 8 dw burst length */
++	lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
++	lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
++	wmb();
++
++	/* toggle reset pin */
++	__gpio_set_value(21, 0);
++	wmb();
++	mdelay(1);
++	__gpio_set_value(21, 1);
++	return 0;
++}
++
++int __init
++pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
++	switch(slot)
++	{
++		case 13:
++			/* IDSEL = AD29 --> USB Host Controller */
++			return (INT_NUM_IM1_IRL0 + 17);
++		case 14:
++			/* IDSEL = AD30 --> mini PCI connector */
++			return (INT_NUM_IM0_IRL0 + 22);
++		default:
++			printk("lq_pci: no IRQ found for slot %d, pin %d\n", slot, pin);
++			return 0;
++	}
++}
++
++static int
++lq_pci_probe(struct platform_device *pdev)
++{
++	struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data;
++	extern int pci_probe_only;
++
++	pci_probe_only = 0;
++	lq_pci_req_mask = lq_pci_data->req_mask;
++	lq_pci_setup_clk(lq_pci_data->clock);
++
++	lq_pci_startup();
++	lq_pci_mapped_cfg =
++		(u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_BASE);
++	lq_pci_controller.io_map_base =
++		(unsigned long)ioremap(LQ_PCI_IO_BASE, LQ_PCI_IO_SIZE - 1);
++
++	register_pci_controller(&lq_pci_controller);
++	return 0;
++}
++
++static struct platform_driver
++lq_pci_driver = {
++	.probe = lq_pci_probe,
++	.driver = {
++		.name = "lq_pci",
++		.owner = THIS_MODULE,
++	},
++};
++
++int __init
++pcibios_init(void)
++{
++	int ret = platform_driver_register(&lq_pci_driver);
++	if(ret)
++		printk(KERN_INFO "lq_pci: Error registering platfom driver!");
++	return ret;
++}
++
++arch_initcall(pcibios_init);