adds new lantiq kernel. once the codebase is fully tested and know to be working on all the devices previously supported by ifxmips, we will drop ifxmips support.

SVN-Revision: 24526

1 files changed, 641 insertions, 0 deletions

diff --git a/target/linux/lantiq/patches/100-board.patch b/target/linux/lantiq/patches/100-board.patch
new file mode 100644
index 0000000000..201fa96737
--- /dev/null
+++ b/target/linux/lantiq/patches/100-board.patch
@@ -0,0 +1,641 @@
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -139,6 +139,9 @@ config MACH_DECSTATION
+ 
+ 	  otherwise choose R3000.
+ 
++config LANTIQ
++	bool "Lantiq MIPS"
++
+ config MACH_JAZZ
+ 	bool "Jazz family of machines"
+ 	select ARC
+@@ -693,6 +696,7 @@ source "arch/mips/txx9/Kconfig"
+ source "arch/mips/vr41xx/Kconfig"
+ source "arch/mips/cavium-octeon/Kconfig"
+ source "arch/mips/loongson/Kconfig"
++source "arch/mips/lantiq/Kconfig"
+ 
+ endmenu
+ 
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -317,6 +317,17 @@ cflags-$(CONFIG_MIPS_COBALT)	+= -I$(srct
+ load-$(CONFIG_MIPS_COBALT)	+= 0xffffffff80080000
+ 
+ #
++# Lantiq
++#
++load-$(CONFIG_LANTIQ) += 0xffffffff80002000
++core-$(CONFIG_LANTIQ) += arch/mips/lantiq/
++cflags-$(CONFIG_LANTIQ)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq
++core-$(CONFIG_SOC_LANTIQ_FALCON) += arch/mips/lantiq/falcon/
++cflags-$(CONFIG_SOC_LANTIQ_FALCON)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
++core-$(CONFIG_SOC_LANTIQ_XWAY) += arch/mips/lantiq/xway/
++cflags-$(CONFIG_SOC_LANTIQ_XWAY)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
++
++#
+ # DECstation family
+ #
+ core-$(CONFIG_MACH_DECSTATION)	+= arch/mips/dec/
+--- /dev/null
++++ b/arch/mips/lantiq/Kconfig
+@@ -0,0 +1,36 @@
++if LANTIQ
++
++config SOC_LANTIQ
++	bool
++	select DMA_NONCOHERENT
++	select IRQ_CPU
++	select CEVT_R4K
++	select CSRC_R4K
++	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_HAS_CPU_MIPS32_R2
++	select SYS_SUPPORTS_BIG_ENDIAN
++	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_MULTITHREADING
++	select SYS_HAS_EARLY_PRINTK
++	select HW_HAS_PCI
++	select ARCH_REQUIRE_GPIOLIB
++	select SWAP_IO_SPACE
++	select MIPS_MACHINE
++
++choice
++	prompt "SoC Type"
++	default SOC_LANTIQ_XWAY
++
++#config SOC_LANTIQ_FALCON
++#	bool "FALCON"
++#	select SOC_LANTIQ
++
++config SOC_LANTIQ_XWAY
++	bool "XWAY"
++	select SOC_LANTIQ
++endchoice
++
++#source "arch/mips/lantiq/falcon/Kconfig"
++source "arch/mips/lantiq/xway/Kconfig"
++
++endif
+--- /dev/null
++++ b/arch/mips/lantiq/Makefile
+@@ -0,0 +1,2 @@
++obj-y := irq.o setup.o clk.o prom.o
++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+--- /dev/null
++++ b/arch/mips/lantiq/irq.c
+@@ -0,0 +1,212 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/interrupt.h>
++
++#include <asm/bootinfo.h>
++#include <asm/irq_cpu.h>
++
++#include <lantiq.h>
++#include <irq.h>
++
++#define LQ_ICU_BASE_ADDR	(KSEG1 | 0x1F880200)
++
++#define LQ_ICU_IM0_ISR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
++#define LQ_ICU_IM0_IER		((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
++#define LQ_ICU_IM0_IOSR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
++#define LQ_ICU_IM0_IRSR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
++#define LQ_ICU_IM0_IMR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
++
++#define LQ_ICU_IM1_ISR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
++#define LQ_ICU_IM2_ISR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
++#define LQ_ICU_IM3_ISR		((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
++#define LQ_ICU_IM4_ISR		((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
++
++#define LQ_ICU_OFFSET		(LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
++
++void
++lq_disable_irq(unsigned int irq_nr)
++{
++	u32 *ier = LQ_ICU_IM0_IER;
++	irq_nr -= INT_NUM_IRQ0;
++	ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
++	irq_nr %= INT_NUM_IM_OFFSET;
++	lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
++}
++EXPORT_SYMBOL(lq_disable_irq);
++
++void
++lq_mask_and_ack_irq(unsigned int irq_nr)
++{
++	u32 *ier = LQ_ICU_IM0_IER;
++	u32 *isr = LQ_ICU_IM0_ISR;
++	irq_nr -= INT_NUM_IRQ0;
++	ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
++	isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
++	irq_nr %= INT_NUM_IM_OFFSET;
++	lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
++	lq_w32((1 << irq_nr), isr);
++}
++EXPORT_SYMBOL(lq_mask_and_ack_irq);
++
++static void
++lq_ack_irq(unsigned int irq_nr)
++{
++	u32 *isr = LQ_ICU_IM0_ISR;
++	irq_nr -= INT_NUM_IRQ0;
++	isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
++	irq_nr %= INT_NUM_IM_OFFSET;
++	lq_w32((1 << irq_nr), isr);
++}
++
++void
++lq_enable_irq(unsigned int irq_nr)
++{
++	u32 *ier = LQ_ICU_IM0_IER;
++	irq_nr -= INT_NUM_IRQ0;
++	ier += LQ_ICU_OFFSET  * (irq_nr / INT_NUM_IM_OFFSET);
++	irq_nr %= INT_NUM_IM_OFFSET;
++	lq_w32(lq_r32(ier) | (1 << irq_nr), ier);
++}
++EXPORT_SYMBOL(lq_enable_irq);
++
++static unsigned int
++lq_startup_irq(unsigned int irq)
++{
++	lq_enable_irq(irq);
++	return 0;
++}
++
++static void
++lq_end_irq(unsigned int irq)
++{
++	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
++		lq_enable_irq(irq);
++}
++
++static struct irq_chip
++lq_irq_type = {
++	"lq_irq",
++	.startup = lq_startup_irq,
++	.enable = lq_enable_irq,
++	.disable = lq_disable_irq,
++	.unmask = lq_enable_irq,
++	.ack = lq_ack_irq,
++	.mask = lq_disable_irq,
++	.mask_ack = lq_mask_and_ack_irq,
++	.end = lq_end_irq,
++};
++
++static void
++lq_hw_irqdispatch(int module)
++{
++	u32 irq;
++
++	irq = lq_r32(LQ_ICU_IM0_IOSR + (module * LQ_ICU_OFFSET));
++	if (irq == 0)
++		return;
++
++	/* silicon bug causes only the msb set to 1 to be valid. all
++	   other bits might be bogus */
++	irq = __fls(irq);
++	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
++}
++
++#define DEFINE_HWx_IRQDISPATCH(x) \
++static void lq_hw ## x ## _irqdispatch(void)\
++{\
++	lq_hw_irqdispatch(x); \
++}
++static void lq_hw5_irqdispatch(void)
++{
++	do_IRQ(MIPS_CPU_TIMER_IRQ);
++}
++DEFINE_HWx_IRQDISPATCH(0)
++DEFINE_HWx_IRQDISPATCH(1)
++DEFINE_HWx_IRQDISPATCH(2)
++DEFINE_HWx_IRQDISPATCH(3)
++DEFINE_HWx_IRQDISPATCH(4)
++/*DEFINE_HWx_IRQDISPATCH(5)*/
++
++asmlinkage void
++plat_irq_dispatch(void)
++{
++	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
++	unsigned int i;
++
++	if (pending & CAUSEF_IP7)
++	{
++		do_IRQ(MIPS_CPU_TIMER_IRQ);
++		goto out;
++	} else {
++		for (i = 0; i < 5; i++)
++		{
++			if (pending & (CAUSEF_IP2 << i))
++			{
++				lq_hw_irqdispatch(i);
++				goto out;
++			}
++		}
++	}
++	printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
++
++out:
++	return;
++}
++
++static struct irqaction
++cascade = {
++	.handler = no_action,
++	.flags = IRQF_DISABLED,
++	.name = "cascade",
++};
++
++void __init
++arch_init_irq(void)
++{
++	int i;
++
++	for (i = 0; i < 5; i++)
++		lq_w32(0, LQ_ICU_IM0_IER + (i * LQ_ICU_OFFSET));
++
++	mips_cpu_irq_init();
++
++	for (i = 2; i <= 6; i++)
++		setup_irq(i, &cascade);
++
++	if (cpu_has_vint) {
++		printk(KERN_INFO "Setting up vectored interrupts\n");
++		set_vi_handler(2, lq_hw0_irqdispatch);
++		set_vi_handler(3, lq_hw1_irqdispatch);
++		set_vi_handler(4, lq_hw2_irqdispatch);
++		set_vi_handler(5, lq_hw3_irqdispatch);
++		set_vi_handler(6, lq_hw4_irqdispatch);
++		set_vi_handler(7, lq_hw5_irqdispatch);
++	}
++
++	for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
++		set_irq_chip_and_handler(i, &lq_irq_type,
++			handle_level_irq);
++
++	#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
++	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
++		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
++	#else
++	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
++		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
++	#endif
++}
++
++void __cpuinit
++arch_fixup_c0_irqs(void)
++{
++	/* FIXME: check for CPUID and only do fix for specific chips/versions */
++	cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
++	cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
++}
+--- /dev/null
++++ b/arch/mips/lantiq/setup.c
+@@ -0,0 +1,47 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++
++#include <lantiq.h>
++#include <lantiq_regs.h>
++
++void __init
++plat_mem_setup(void)
++{
++	/* assume 16M as default */
++	int memsize = 16;
++	char **envp = (char **) KSEG1ADDR(fw_arg2);
++	u32 status;
++
++	/* make sure to have no "reverse endian" for user mode! */
++	status = read_c0_status();
++	status &= (~(1<<25));
++	write_c0_status(status);
++
++	ioport_resource.start = IOPORT_RESOURCE_START;
++	ioport_resource.end = IOPORT_RESOURCE_END;
++	iomem_resource.start = IOMEM_RESOURCE_START;
++	iomem_resource.end = IOMEM_RESOURCE_END;
++
++	while (*envp)
++	{
++		char *e = (char *)KSEG1ADDR(*envp);
++		if (!strncmp(e, "memsize=", 8))
++		{
++			e += 8;
++			memsize = simple_strtoul(e, NULL, 10);
++		}
++		envp++;
++	}
++	memsize *= 1024 * 1024;
++	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
++}
+--- /dev/null
++++ b/arch/mips/lantiq/clk.c
+@@ -0,0 +1,141 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/list.h>
++
++#include <asm/time.h>
++#include <asm/irq.h>
++#include <asm/div64.h>
++
++#include <lantiq.h>
++#ifdef CONFIG_SOC_LANTIQ_XWAY
++#include <xway.h>
++#endif
++
++extern unsigned long lq_get_cpu_hz(void);
++extern unsigned long lq_get_fpi_hz(void);
++extern unsigned long lq_get_io_region_clock(void);
++
++struct clk {
++	const char *name;
++	unsigned long rate;
++	unsigned long (*get_rate) (void);
++};
++
++static struct clk *cpu_clk = 0;
++static int cpu_clk_cnt = 0;
++
++static unsigned int r4k_offset;
++static unsigned int r4k_cur;
++
++static struct clk cpu_clk_generic[] = {
++	{
++		.name = "cpu",
++		.get_rate = lq_get_cpu_hz,
++	}, {
++		.name = "fpi",
++		.get_rate = lq_get_fpi_hz,
++	}, {
++		.name = "io",
++		.get_rate = lq_get_io_region_clock,
++	},
++};
++
++void
++clk_init(void)
++{
++	int i;
++	cpu_clk = cpu_clk_generic;
++	cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
++	for(i = 0; i < cpu_clk_cnt; i++)
++		printk("%s: %ld\n", cpu_clk[i].name, clk_get_rate(&cpu_clk[i]));
++}
++
++static inline int
++clk_good(struct clk *clk)
++{
++	return clk && !IS_ERR(clk);
++}
++
++unsigned long
++clk_get_rate(struct clk *clk)
++{
++	if (unlikely(!clk_good(clk)))
++		return 0;
++
++	if (clk->rate != 0)
++		return clk->rate;
++
++	if (clk->get_rate != NULL)
++		return clk->get_rate();
++
++	return 0;
++}
++EXPORT_SYMBOL(clk_get_rate);
++
++struct clk*
++clk_get(struct device *dev, const char *id)
++{
++	int i;
++	for(i = 0; i < cpu_clk_cnt; i++)
++		if (!strcmp(id, cpu_clk[i].name))
++			return &cpu_clk[i];
++	BUG();
++	return ERR_PTR(-ENOENT);
++}
++EXPORT_SYMBOL(clk_get);
++
++void
++clk_put(struct clk *clk)
++{
++	/* not used */
++}
++EXPORT_SYMBOL(clk_put);
++
++static inline u32
++lq_get_counter_resolution(void)
++{
++	u32 res;
++	__asm__ __volatile__(
++		".set   push\n"
++		".set   mips32r2\n"
++		".set   noreorder\n"
++		"rdhwr  %0, $3\n"
++		"ehb\n"
++		".set pop\n"
++		: "=&r" (res)
++		: /* no input */
++		: "memory");
++	instruction_hazard();
++	return res;
++}
++
++void __init
++plat_time_init(void)
++{
++	struct clk *clk = clk_get(0, "cpu");
++	mips_hpt_frequency = clk_get_rate(clk) / lq_get_counter_resolution();
++	r4k_cur = (read_c0_count() + r4k_offset);
++	write_c0_compare(r4k_cur);
++
++#ifdef CONFIG_SOC_LANTIQ_XWAY
++#define LQ_GPTU_GPT_CLC			((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
++	lq_pmu_enable(PMU_GPT);
++	lq_pmu_enable(PMU_FPI);
++
++	lq_w32(0x100, LQ_GPTU_GPT_CLC);
++#endif
++}
+--- /dev/null
++++ b/arch/mips/lantiq/prom.c
+@@ -0,0 +1,118 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <asm/bootinfo.h>
++#include <asm/time.h>
++
++#include <lantiq.h>
++
++#include "prom.h"
++
++static struct lq_soc_info soc_info;
++
++/* for Multithreading (APRP) on MIPS34K */
++unsigned long physical_memsize;
++
++/* all access to the ebu must be locked */
++DEFINE_SPINLOCK(ebu_lock);
++EXPORT_SYMBOL_GPL(ebu_lock);
++
++extern void clk_init(void);
++
++unsigned int
++lq_get_cpu_ver(void)
++{
++	return soc_info.rev;
++}
++EXPORT_SYMBOL(lq_get_cpu_ver);
++
++unsigned int
++lq_get_soc_type(void)
++{
++	return soc_info.type;
++}
++EXPORT_SYMBOL(lq_get_soc_type);
++
++const char*
++get_system_type(void)
++{
++	return soc_info.sys_type;
++}
++
++void
++prom_free_prom_memory(void)
++{
++}
++
++#ifdef CONFIG_IMAGE_CMDLINE_HACK
++extern char __image_cmdline[];
++
++static void __init
++prom_init_image_cmdline(void)
++{
++	char *p = __image_cmdline;
++	int replace = 0;
++
++	if (*p == '-') {
++		replace = 1;
++		p++;
++	}
++
++	if (*p == '\0')
++		return;
++
++	if (replace) {
++		strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
++	} else {
++		strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
++		strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
++	}
++}
++#else
++static void __init prom_init_image_cmdline(void) { return; }
++#endif
++
++static void __init
++prom_init_cmdline(void)
++{
++	int argc = fw_arg0;
++	char **argv = (char**)KSEG1ADDR(fw_arg1);
++	int i;
++
++	arcs_cmdline[0] = '\0';
++	if(argc)
++		for (i = 1; i < argc; i++)
++		{
++			strlcat(arcs_cmdline, (char*)KSEG1ADDR(argv[i]), COMMAND_LINE_SIZE);
++			if(i + 1 != argc)
++				strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
++		}
++
++	if (!*arcs_cmdline)
++		strcpy(&(arcs_cmdline[0]),
++			"console=ttyS1,115200 rootfstype=squashfs,jffs2");
++	prom_init_image_cmdline();
++}
++
++void __init
++prom_init(void)
++{
++	struct clk *clk;
++	lq_soc_detect(&soc_info);
++
++	clk_init();
++	clk = clk_get(0, "cpu");
++	snprintf(soc_info.sys_type, LQ_SYS_TYPE_LEN - 1, "%s rev1.%d %ldMhz",
++		soc_info.name, soc_info.rev, clk_get_rate(clk) / 1000000);
++	soc_info.sys_type[LQ_SYS_TYPE_LEN - 1] = '\0';
++	printk("SoC: %s\n", soc_info.sys_type);
++
++	prom_init_cmdline();
++}
+--- /dev/null
++++ b/arch/mips/lantiq/prom.h
+@@ -0,0 +1,24 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _LQ_PROM_H__
++#define _LQ_PROM_H__
++
++#define LQ_SYS_TYPE_LEN	0x100
++
++struct lq_soc_info {
++	unsigned char *name;
++	unsigned int rev;
++	unsigned int partnum;
++	unsigned int type;
++	unsigned char sys_type[LQ_SYS_TYPE_LEN];
++};
++
++void lq_soc_detect(struct lq_soc_info *i);
++
++#endif