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| author | John Crispin <john@openwrt.org> | 2015-07-07 13:43:47 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-07-07 13:43:47 +0000 |
| commit | ff08b0957026645e436c3388aa3f3f0032765106 (patch) | |
| tree | bd023d085ea8774e977bc7200bf396eb7b1dca78 /target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch | |
| parent | 2658b33f68403dfc39b7cab6d27b9140284b6b92 (diff) | |
| download | upstream-ff08b0957026645e436c3388aa3f3f0032765106.tar.gz upstream-ff08b0957026645e436c3388aa3f3f0032765106.tar.bz2 upstream-ff08b0957026645e436c3388aa3f3f0032765106.zip | |
lantiq: Add support for linux 4.1
All (still relevant) patches were refresh.
The following patches were dropped because they are applied upstream:
- 0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch
- 0005-MIPS-lantiq-add-reset-controller-api-support.patch
- 0006-MIPS-lantiq-reboot-gphy-on-restart.patch
- 0009-MIPS-lantiq-command-line-work-around.patch
- 0010-MIPS-lantiq-export-soc-type.patch
- 0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch
- 0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 46216
Diffstat (limited to 'target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch')
| -rw-r--r-- | target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch b/target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch new file mode 100644 index 0000000000..d43cdf3d54 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch @@ -0,0 +1,23 @@ +From 08b085a07efe12568d86dff064e6f089e2971744 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Date: Mon, 25 May 2015 22:39:50 +0200 +Subject: gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs + +0x3 only masks two bits, but three bits have to be allowed. This fixes +GPHY0 LED2 (which is the highest bit of phy2) on my board. + +Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Acked-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Linus Walleij <linus.walleij@linaro.org> + +--- a/drivers/gpio/gpio-stp-xway.c ++++ b/drivers/gpio/gpio-stp-xway.c +@@ -58,7 +58,7 @@ + #define XWAY_STP_ADSL_MASK 0x3 + + /* 2 groups of 3 bits can be driven by the phys */ +-#define XWAY_STP_PHY_MASK 0x3 ++#define XWAY_STP_PHY_MASK 0x7 + #define XWAY_STP_PHY1_SHIFT 27 + #define XWAY_STP_PHY2_SHIFT 15 + |