lantiq: Add support for linux 4.1

All (still relevant) patches were refresh.
The following patches were dropped because they are applied upstream:
- 0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch
- 0005-MIPS-lantiq-add-reset-controller-api-support.patch
- 0006-MIPS-lantiq-reboot-gphy-on-restart.patch
- 0009-MIPS-lantiq-command-line-work-around.patch
- 0010-MIPS-lantiq-export-soc-type.patch
- 0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch
- 0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 46216

1 files changed, 44 insertions, 0 deletions

diff --git a/target/linux/lantiq/patches-4.1/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch b/target/linux/lantiq/patches-4.1/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch
new file mode 100644
index 0000000000..6a7785b016
--- /dev/null
+++ b/target/linux/lantiq/patches-4.1/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch
@@ -0,0 +1,44 @@
+From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 18:06:39 +0200
+Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be
+ persistent
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/xway_nand.c |   12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/mtd/nand/xway_nand.c
++++ b/drivers/mtd/nand/xway_nand.c
+@@ -54,6 +54,8 @@
+ #define NAND_CON_CSMUX		(1 << 1)
+ #define NAND_CON_NANDM		1
+ 
++static u32 xway_latchcmd;
++
+ static void xway_reset_chip(struct nand_chip *chip)
+ {
+ 	unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
+@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf
+ 	unsigned long flags;
+ 
+ 	if (ctrl & NAND_CTRL_CHANGE) {
+-		nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
+ 		if (ctrl & NAND_CLE)
+-			nandaddr |= NAND_WRITE_CMD;
+-		else
+-			nandaddr |= NAND_WRITE_ADDR;
+-		this->IO_ADDR_W = (void __iomem *) nandaddr;
++			xway_latchcmd = NAND_WRITE_CMD;
++		else if (ctrl & NAND_ALE)
++			xway_latchcmd = NAND_WRITE_ADDR;
+ 	}
+ 
+ 	if (cmd != NAND_CMD_NONE) {
+ 		spin_lock_irqsave(&ebu_lock, flags);
+-		writeb(cmd, this->IO_ADDR_W);
++		writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
+ 		while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ 			;
+ 		spin_unlock_irqrestore(&ebu_lock, flags);