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| author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-04-02 23:40:10 +0200 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2021-07-19 14:51:22 +0200 |
| commit | 939c0030dba2742e17e18b68999e23317796ace8 (patch) | |
| tree | 1952aecf13236a620aa1eb056e028741b444f205 /target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi | |
| parent | 0458a8993ca1c1594bc19d247909324f157abeef (diff) | |
| download | upstream-939c0030dba2742e17e18b68999e23317796ace8.tar.gz upstream-939c0030dba2742e17e18b68999e23317796ace8.tar.bz2 upstream-939c0030dba2742e17e18b68999e23317796ace8.zip | |
lantiq: convert mtd-mac-address to nvmem implementation
Define nvmem-cells and convert mtd-mac-address to nvmem implementation.
The conversion is done with an automated script.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi')
| -rw-r--r-- | target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi index 67edc01d90..e37f1ab37c 100644 --- a/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi +++ b/target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi @@ -100,7 +100,8 @@ }; ð0 { - mtd-mac-address = <&romfile 0xf100>; + nvmem-cells = <&macaddr_romfile_f100>; + nvmem-cell-names = "mac-address"; }; &gphy0 { @@ -191,7 +192,8 @@ mediatek,mtd-eeprom = <&radio 0x0000>; big-endian; ieee80211-freq-limit = <5000000 6000000>; - mtd-mac-address = <&romfile 0xf100>; + nvmem-cells = <&macaddr_romfile_f100>; + nvmem-cell-names = "mac-address"; mac-address-increment = <2>; }; }; @@ -277,3 +279,13 @@ status = "okay"; vbus-supply = <&usb_vbus>; }; + +&romfile { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_romfile_f100: macaddr@f100 { + reg = <0xf100 0x6>; + }; +}; |