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authorFelix Fietkau <nbd@openwrt.org>2016-01-17 19:55:10 +0000
committerFelix Fietkau <nbd@openwrt.org>2016-01-17 19:55:10 +0000
commit3f8a4260564d70bd2df9b417b4d03ec39422b8f5 (patch)
tree202a2d6321ba1f4015d309469de97a00103e3a83 /target/linux/lantiq/dts/vr9.dtsi
parent1204a1b1e55a3d1e0ff7b0309c414fb0a1f38eda (diff)
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lantiq: Configure the PCIe reset GPIO using OF
After the latest pinctrl backports there are only 50 (instead of 56 as before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now 462, before it was 456). This means that any hardcoded GPIOs have to be adjusted. This broke the PCIe driver (which seems to be the only driver which uses hardcoded GPIO numbers), it only reports: ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout ifx_pcie_wait_phy_link_up timeout pcie_rc_initialize link up failed!!!!! To prevent more of these issues in the future we remove the hardcoded PCIe reset GPIO definition and simply pass it via device-tree (like the PCI driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48285
Diffstat (limited to 'target/linux/lantiq/dts/vr9.dtsi')
-rw-r--r--target/linux/lantiq/dts/vr9.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/lantiq/dts/vr9.dtsi b/target/linux/lantiq/dts/vr9.dtsi
index 8f9635807e..2330bf1c21 100644
--- a/target/linux/lantiq/dts/vr9.dtsi
+++ b/target/linux/lantiq/dts/vr9.dtsi
@@ -175,6 +175,7 @@
interrupt-parent = <&icu0>;
interrupts = <161 144>;
compatible = "lantiq,pcie-xrx200";
+ gpio-reset = <&gpio 38 0>;
};
pci0: pci@E105400 {