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authorPavel Kubelun <be.dissent@gmail.com>2018-01-18 13:51:25 +0300
committerJohn Crispin <john@phrozen.org>2018-05-22 20:34:14 +0200
commitfbedc2213c19023bb4ec4ed7bd71908501aaf6d1 (patch)
treee1ca154dd1966eac766ade20f75272798f59f42a /target/linux/ipq806x
parentd4b98c38c6acdabf37c9d099be5e2c3cf06a05fb (diff)
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ipq806x: fix pcie tx termination offset
According to GPL tarballs and QSDK related branch tx termination offset for ipq8064 SoC version >= 2.0 should be equal to 0 and not 7. https://github.com/paul-chambers/netgear-r7800/blob/master/git_home/linux.git/sourcecode/arch/arm/mach-msm/board-ipq806x.c#L1682-L1685 Fix this. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Diffstat (limited to 'target/linux/ipq806x')
-rw-r--r--target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi12
-rw-r--r--target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi12
2 files changed, 24 insertions, 0 deletions
diff --git a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
index 5a40b03eef..8c522a897d 100644
--- a/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
+++ b/target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -14,5 +14,17 @@
tx_deamp_3_5db = <32>;
mpll = <0xa0>;
};
+
+ pcie0: pci@1b500000 {
+ phy-tx0-term-offset = <0>;
+ };
+
+ pcie1: pci@1b700000 {
+ phy-tx0-term-offset = <0>;
+ };
+
+ pcie2: pci@1b900000 {
+ phy-tx0-term-offset = <0>;
+ };
};
};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
index 5a40b03eef..8c522a897d 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -14,5 +14,17 @@
tx_deamp_3_5db = <32>;
mpll = <0xa0>;
};
+
+ pcie0: pci@1b500000 {
+ phy-tx0-term-offset = <0>;
+ };
+
+ pcie1: pci@1b700000 {
+ phy-tx0-term-offset = <0>;
+ };
+
+ pcie2: pci@1b900000 {
+ phy-tx0-term-offset = <0>;
+ };
};
};