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authorMarc Benoit <marcb62185@gmail.com>2018-04-04 18:57:50 -0400
committerJohn Crispin <john@phrozen.org>2018-05-22 20:34:14 +0200
commite40db2907e2a7d4837b25be3bedb1f25fc248bbf (patch)
treeb209ee376796646e815e034bea2043ffb0718476 /target/linux/ipq806x
parent05f53eecca5e1b28706ef074477a55917ed6deb1 (diff)
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kernel: iqp806x low latency kernel does not boot
It keeps failing (R7800) with the stack trace below BUG: scheduling while atomic: kworker/0:1/26/0x00000002 (unwind_backtrace) from [<c02121d0>] (show_stack+0x10/0x14) (show_stack) from [<c03932e4>] (dump_stack+0x7c/0x9c) (dump_stack) from [<c0239b90>] (__schedule_bug+0x5c/0x80) (__schedule_bug) from [<c05b7260>] (__schedule+0x50/0x3f4) (__schedule) from [<c05b76a8>] (schedule+0xa4/0xd4) (schedule) from [<c05ba430>] (schedule_hrtimeout_range_clock+0xc8/0x100) (schedule_hrtimeout_range_clock) from [<c05ba480>] (schedule_hrtimeout_range+0x18/0x20) (schedule_hrtimeout_range) from [<c05b9f78>] (usleep_range+0x48/0x50) (usleep_range) from [<c03f333c>] (__clk_hfpll_enable+0x44/0xd0) (__clk_hfpll_enable) from [<c03f3474>] (clk_hfpll_set_rate+0xac/0xc4) (clk_hfpll_set_rate) from [<c03ec390>] (clk_change_rate+0xf4/0x1fc) (clk_change_rate) from [<c03ec510>] (clk_core_set_rate_nolock+0x78/0x94) (clk_core_set_rate_nolock) from [<c03ec54c>] (clk_set_rate+0x20/0x30) (clk_set_rate) from [<c0424168>] (dev_pm_opp_set_rate+0x190/0x26c) (dev_pm_opp_set_rate) from [<c04a8548>] (set_target+0x40/0x108) (set_target) from [<c04a4.140>] (__cpufreq_driver_target+0x3f4/0x488) (__cpufreq_driver_target) from [<c04a7494>] (od_dbs_timer+0xcc/0x154) (od_dbs_timer) from [<c04a7998>] (dbs_work_handler+0x2c/0x54) (dbs_work_handler) from [<c02309e8>] (process_one_work+0x1c0/0x2f0) (process_one_work) from [<c02319a8>] (worker_thread+0x2a4/0x404) (worker_thread) from [<c0235944>] (kthread+0xd8/0xe8) (kthread) from [<c020eef0>] (ret_from_fork+0x14/0x24) Signed-off-by: Marc Benoit <marcb62185@gmail.com> [slh: rebase for kernel v4.14 as well] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Diffstat (limited to 'target/linux/ipq806x')
-rw-r--r--target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch4
-rw-r--r--target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch4
2 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
index e0157d56b8..f09197caa8 100644
--- a/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
+++ b/target/linux/ipq806x/patches-4.14/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
@@ -117,7 +117,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
-+ usleep_range(10, 100);
++ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
@@ -128,7 +128,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+ regmap_read(regmap, hd->status_reg, &val);
+ } while (!(val & BIT(hd->lock_bit)));
+ } else {
-+ usleep_range(60, 100);
++ udelay(60);
+ }
+
+ /* Enable PLL output. */
diff --git a/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
index 70926143ec..a2067572b1 100644
--- a/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
+++ b/target/linux/ipq806x/patches-4.9/0038-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch
@@ -117,7 +117,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+ * H/W requires a 5us delay between disabling the bypass and
+ * de-asserting the reset. Delay 10us just to be safe.
+ */
-+ usleep_range(10, 100);
++ udelay(10);
+
+ /* De-assert active-low PLL reset. */
+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
@@ -128,7 +128,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+ regmap_read(regmap, hd->status_reg, &val);
+ } while (!(val & BIT(hd->lock_bit)));
+ } else {
-+ usleep_range(60, 100);
++ udelay(60);
+ }
+
+ /* Enable PLL output. */