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| author | Christian Marangi <ansuelsmth@gmail.com> | 2022-06-16 22:14:23 +0200 |
|---|---|---|
| committer | Christian Marangi <ansuelsmth@gmail.com> | 2022-10-11 21:28:41 +0200 |
| commit | cd619eeff2cb18907b69c26ca496f558575de9ba (patch) | |
| tree | 27cdad2c6f9e0c93e185db2d49c048b5b55f94e5 /target/linux/ipq806x | |
| parent | 61a2bedf7902c64a47a42a3d8df3350f1b67ee2f (diff) | |
| download | upstream-cd619eeff2cb18907b69c26ca496f558575de9ba.tar.gz upstream-cd619eeff2cb18907b69c26ca496f558575de9ba.tar.bz2 upstream-cd619eeff2cb18907b69c26ca496f558575de9ba.zip | |
ipq806x: 5.15: replace gcc fixes with upstream version
Replace gcc patch fixes with upstream version.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux/ipq806x')
13 files changed, 1761 insertions, 272 deletions
diff --git a/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch b/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch deleted file mode 100644 index 3b4900fafb..0000000000 --- a/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Sun, 7 Feb 2021 16:52:56 +0100 -Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag - -Some flag are missing from the original code. -These clk can't be set using the protected-clock proprities as they -cause the malfunction of the serial interface. -These clks are needed for the rpm interface to work proprely or the -cpu regulators starts to fail as soon as they are disabled by the -kernel. - -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> ---- - drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -65,6 +65,7 @@ static struct clk_pll pll3 = { - .parent_names = (const char *[]){ "pxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, -+ .flags = CLK_IS_CRITICAL, - }, - }; - -@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk = - .parent_names = (const char *[]){ "gsbi4_qup_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk = - .parent_names = (const char *[]){ "gsbi7_qup_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_h_clk", - .ops = &clk_branch_ops, -+ .flags = CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -+ .flags = CLK_SET_RATE_GATE, - }, - } - }; -@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, -- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | -+ CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, -- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | -+ CLK_IGNORE_UNUSED, - }, - }, - }; diff --git a/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch b/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch deleted file mode 100644 index 78068f359c..0000000000 --- a/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Sun, 7 Feb 2021 17:08:16 +0100 -Subject: [PATCH 3/4] clk: qcom: krait: add missing enable disable - -Add missing enable disable mux function. Add extra check to -div2_round_rate. - -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> ---- - drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++-- - 1 file changed, 25 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -73,7 +73,25 @@ static u8 krait_mux_get_parent(struct cl - return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); - } - -+static int krait_mux_enable(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ -+ __krait_mux_set_sel(mux, mux->en_mask); -+ -+ return 0; -+} -+ -+static void krait_mux_disable(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ -+ __krait_mux_set_sel(mux, mux->safe_sel); -+} -+ - const struct clk_ops krait_mux_clk_ops = { -+ .enable = krait_mux_enable, -+ .disable = krait_mux_disable, - .set_parent = krait_mux_set_parent, - .get_parent = krait_mux_get_parent, - .determine_rate = __clk_mux_determine_rate_closest, -@@ -84,8 +102,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); - static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) - { -- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); -- return DIV_ROUND_UP(*parent_rate, 2); -+ struct clk_hw *hw_parent = clk_hw_get_parent(hw); -+ -+ if (hw_parent) { -+ *parent_rate = clk_hw_round_rate(hw_parent, rate * 2); -+ return DIV_ROUND_UP(*parent_rate, 2); -+ } else -+ return -1; - } - - static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch new file mode 100644 index 0000000000..f3f3ea30da --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-04-linux-next-clk-qcom-gcc-ipq806x-fix-wrong-naming-for-gcc_pxo_pl.patch @@ -0,0 +1,109 @@ +From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:24 +0100 +Subject: [PATCH 04/14] clk: qcom: gcc-ipq806x: fix wrong naming for + gcc_pxo_pll8_pll0 + +Parent gcc_pxo_pll8_pll0 had the parent definition and parent map +swapped. Fix this naming error. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] + "pll3", + }; + +-static const struct parent_map gcc_pxo_pll8_pll0[] = { ++static const struct parent_map gcc_pxo_pll8_pll0_map[] = { + { P_PXO, 0 }, + { P_PLL8, 3 }, + { P_PLL0, 2 } + }; + +-static const char * const gcc_pxo_pll8_pll0_map[] = { ++static const char * const gcc_pxo_pll8_pll0[] = { + "pxo", + "pll8_vote", + "pll0_vote", +@@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_s + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb30_master, + .clkr = { +@@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_master_ref_src", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb30_utmi, + .clkr = { +@@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_utmi_clk", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb, + .clkr = { +@@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + }, + .s = { + .src_sel_shift = 0, +- .parent_map = gcc_pxo_pll8_pll0, ++ .parent_map = gcc_pxo_pll8_pll0_map, + }, + .freq_tbl = clk_tbl_usb, + .clkr = { +@@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0_map, ++ .parent_names = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch new file mode 100644 index 0000000000..d99ac9992f --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-05-linux-next-clk-qcom-gcc-ipq806x-convert-parent_names-to-parent_.patch @@ -0,0 +1,921 @@ +From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:25 +0100 +Subject: [PATCH 05/14] clk: qcom: gcc-ipq806x: convert parent_names to + parent_data + +Convert parent_names to parent_data to modernize the driver. +Where possible use parent_hws directly. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++------------- + 1 file changed, 173 insertions(+), 113 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -25,6 +25,10 @@ + #include "clk-hfpll.h" + #include "reset.h" + ++static const struct clk_parent_data gcc_pxo[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++}; ++ + static struct clk_pll pll0 = { + .l_reg = 0x30c4, + .m_reg = 0x30c8, +@@ -35,7 +39,7 @@ static struct clk_pll pll0 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll0", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "pll0_vote", +- .parent_names = (const char *[]){ "pll0" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pll0.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +@@ -62,7 +68,7 @@ static struct clk_pll pll3 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll3", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -89,7 +95,7 @@ static struct clk_pll pll8 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll8", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "pll8_vote", +- .parent_names = (const char *[]){ "pll8" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pll8.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { + static struct clk_hfpll hfpll0 = { + .d = &hfpll0_data, + .clkr.hw.init = &(struct clk_init_data){ +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .name = "hfpll0", + .ops = &clk_ops_hfpll, +@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { + static struct clk_hfpll hfpll1 = { + .d = &hfpll1_data, + .clkr.hw.init = &(struct clk_init_data){ +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .name = "hfpll1", + .ops = &clk_ops_hfpll, +@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = + static struct clk_hfpll hfpll_l2 = { + .d = &hfpll_l2_data, + .clkr.hw.init = &(struct clk_init_data){ +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .name = "hfpll_l2", + .ops = &clk_ops_hfpll, +@@ -194,7 +202,7 @@ static struct clk_pll pll14 = { + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll14", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "pll14_vote", +- .parent_names = (const char *[]){ "pll14" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pll14.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +@@ -238,7 +248,7 @@ static struct clk_pll pll18 = { + .freq_tbl = pll18_freq_tbl, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll18", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_p + { P_PLL8, 3 } + }; + +-static const char * const gcc_pxo_pll8[] = { +- "pxo", +- "pll8_vote", ++static const struct clk_parent_data gcc_pxo_pll8[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, + }; + + static const struct parent_map gcc_pxo_pll8_cxo_map[] = { +@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_p + { P_CXO, 5 } + }; + +-static const char * const gcc_pxo_pll8_cxo[] = { +- "pxo", +- "pll8_vote", +- "cxo", ++static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .fw_name = "cxo", .name = "cxo" }, + }; + + static const struct parent_map gcc_pxo_pll3_map[] = { +@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_p + { P_PLL3, 6 } + }; + +-static const char * const gcc_pxo_pll3[] = { +- "pxo", +- "pll3", ++static const struct clk_parent_data gcc_pxo_pll3[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll3.clkr.hw }, + }; + + static const struct parent_map gcc_pxo_pll8_pll0_map[] = { +@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_p + { P_PLL0, 2 } + }; + +-static const char * const gcc_pxo_pll8_pll0[] = { +- "pxo", +- "pll8_vote", +- "pll0_vote", ++static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .hw = &pll0_vote.hw }, + }; + + static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { +@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_p + { P_PLL18, 1 } + }; + +-static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { +- "pxo", +- "pll8_vote", +- "pll0_vote", +- "pll14", +- "pll18", ++static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { ++ { .fw_name = "pxo", .name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .hw = &pll0_vote.hw }, ++ { .hw = &pll14.clkr.hw }, ++ { .hw = &pll18.clkr.hw }, + }; + + static struct freq_tbl clk_tbl_gsbi_uart[] = { +@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi1_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi1_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi2_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi2_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi4_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi4_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi5_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi5_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi6_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi6_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_uart_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_uart_clk", +- .parent_names = (const char *[]){ +- "gsbi7_uart_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi7_uart_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_qup_clk", +- .parent_names = (const char *[]){ "gsbi1_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi1_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_qup_clk", +- .parent_names = (const char *[]){ "gsbi2_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi2_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_qup_clk", +- .parent_names = (const char *[]){ "gsbi4_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi4_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_qup_clk", +- .parent_names = (const char *[]){ "gsbi5_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi5_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_qup_clk", +- .parent_names = (const char *[]){ "gsbi6_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi6_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_qup_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_qup_clk", +- .parent_names = (const char *[]){ "gsbi7_qup_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gsbi7_qup_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gp0_src", +- .parent_names = gcc_pxo_pll8_cxo, ++ .parent_data = gcc_pxo_pll8_cxo, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, +@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gp0_clk", +- .parent_names = (const char *[]){ "gp0_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp0_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gp1_src", +- .parent_names = gcc_pxo_pll8_cxo, ++ .parent_data = gcc_pxo_pll8_cxo, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gp1_clk", +- .parent_names = (const char *[]){ "gp1_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp1_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gp2_src", +- .parent_names = gcc_pxo_pll8_cxo, ++ .parent_data = gcc_pxo_pll8_cxo, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gp2_clk", +- .parent_names = (const char *[]){ "gp2_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &gp2_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "prng_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "prng_clk", +- .parent_names = (const char *[]){ "prng_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &prng_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + }, +@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "sdc1_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "sdc1_clk", +- .parent_names = (const char *[]){ "sdc1_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdc1_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "sdc3_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "sdc3_clk", +- .parent_names = (const char *[]){ "sdc3_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sdc3_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "tsif_ref_src", +- .parent_names = gcc_pxo_pll8, ++ .parent_data = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, + }, +@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "tsif_ref_clk", +- .parent_names = (const char *[]){ "tsif_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &tsif_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcie_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_cl + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcie_ref_src_clk", +- .parent_names = (const char *[]){ "pcie_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcie1_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_c + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcie1_ref_src_clk", +- .parent_names = (const char *[]){ "pcie1_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie1_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "pcie2_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_c + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "pcie2_ref_src_clk", +- .parent_names = (const char *[]){ "pcie2_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &pcie2_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "sata_ref_src", +- .parent_names = gcc_pxo_pll3, ++ .parent_data = gcc_pxo_pll3, + .num_parents = 2, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "sata_rxoob_clk", +- .parent_names = (const char *[]){ "sata_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sata_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "sata_pmalive_clk", +- .parent_names = (const char *[]){ "sata_ref_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &sata_ref_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "sata_phy_ref_clk", +- .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = gcc_pxo, + .num_parents = 1, + .ops = &clk_branch_ops, + }, +@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_master_ref_src", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_ + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_0_branch_clk", +- .parent_names = (const char *[]){ "usb30_master_ref_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_ + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_1_branch_clk", +- .parent_names = (const char *[]){ "usb30_master_ref_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_master_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb30_utmi_clk", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_0_utmi_clk_ctl", +- .parent_names = (const char *[]){ "usb30_utmi_clk", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_utmi_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_cl + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb30_1_utmi_clk_ctl", +- .parent_names = (const char *[]){ "usb30_utmi_clk", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb30_utmi_clk.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_cl + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_clk", +- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb_hs1_xcvr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_src", +- .parent_names = gcc_pxo_pll8_pll0, ++ .parent_data = gcc_pxo_pll8_pll0, + .num_parents = 3, + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, +@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_cl + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_clk", +- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb_fs1_xcvr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_sys_clk", +- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, ++ .parent_hws = (const struct clk_hw*[]){ ++ &usb_fs1_xcvr_clk_src.clkr.hw, ++ }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, +@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_clk", +- .parent_names = (const char *[]){ +- "gmac_core1_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core1_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_clk", +- .parent_names = (const char *[]){ +- "gmac_core2_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core2_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_clk", +- .parent_names = (const char *[]){ +- "gmac_core3_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core3_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_clk", +- .parent_names = (const char *[]){ +- "gmac_core4_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &gmac_core4_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_src", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + }, +@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { + .enable_mask = BIT(6) | BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_clk", +- .parent_names = (const char *[]){ +- "nss_tcm_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &nss_tcm_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, +@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_sr + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core1_src_clk", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, +@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_sr + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core2_src_clk", +- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, + .num_parents = 5, + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch new file mode 100644 index 0000000000..6e6cec7db5 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-06-linux-next-clk-qcom-gcc-ipq806x-use-ARRAY_SIZE-for-num_parents.patch @@ -0,0 +1,325 @@ +From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:26 +0100 +Subject: [PATCH 06/14] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents + +Use ARRAY_SIZE for num_parents instead of hardcoding the value. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++----------------- + 1 file changed, 34 insertions(+), 34 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_uart_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi1_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi2_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi5_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi6_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi7_qup_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { + .hw.init = &(struct clk_init_data){ + .name = "gp0_src", + .parent_data = gcc_pxo_pll8_cxo, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), + .ops = &clk_rcg_ops, + .flags = CLK_SET_PARENT_GATE, + }, +@@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { + .hw.init = &(struct clk_init_data){ + .name = "gp1_src", + .parent_data = gcc_pxo_pll8_cxo, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { + .hw.init = &(struct clk_init_data){ + .name = "gp2_src", + .parent_data = gcc_pxo_pll8_cxo, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { + .hw.init = &(struct clk_init_data){ + .name = "prng_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + }, +@@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { + .hw.init = &(struct clk_init_data){ + .name = "sdc1_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + } +@@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { + .hw.init = &(struct clk_init_data){ + .name = "sdc3_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + } +@@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "tsif_ref_src", + .parent_data = gcc_pxo_pll8, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, + }, + } +@@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "pcie_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "pcie1_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "pcie2_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { + .hw.init = &(struct clk_init_data){ + .name = "sata_ref_src", + .parent_data = gcc_pxo_pll3, +- .num_parents = 2, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_s + .hw.init = &(struct clk_init_data){ + .name = "usb30_master_ref_src", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { + .hw.init = &(struct clk_init_data){ + .name = "usb30_utmi_clk", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_s + .hw.init = &(struct clk_init_data){ + .name = "usb_hs1_xcvr_src", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_s + .hw.init = &(struct clk_init_data){ + .name = "usb_fs1_xcvr_src", + .parent_data = gcc_pxo_pll8_pll0, +- .num_parents = 3, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), + .ops = &clk_rcg_ops, + .flags = CLK_SET_RATE_GATE, + }, +@@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core1_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core2_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core3_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src + .hw.init = &(struct clk_init_data){ + .name = "gmac_core4_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = + .hw.init = &(struct clk_init_data){ + .name = "nss_tcm_src", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + }, + }, +@@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_sr + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core1_src_clk", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, +@@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_sr + .hw.init = &(struct clk_init_data){ + .name = "ubi32_core2_src_clk", + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, +- .num_parents = 5, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), + .ops = &clk_dyn_rcg_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch new file mode 100644 index 0000000000..b0f09ec34d --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-07-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-nss-cores.patch @@ -0,0 +1,88 @@ +From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:27 +0100 +Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores + +Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be +clocked to 800MHz. Add these missing freq to the gcc driver. +Set the freq_tbl for the ubi32_cores to the correct values based on the +machine compatible. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++--- + 1 file changed, 21 insertions(+), 3 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { + + static struct pll_freq_tbl pll18_freq_tbl[] = { + NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), ++ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), + NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), ++ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), + }; + + static struct clk_pll pll18 = { +@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = { + }, + }; + +-static const struct freq_tbl clk_tbl_nss[] = { ++static const struct freq_tbl clk_tbl_nss_ipq8064[] = { + { 110000000, P_PLL18, 1, 1, 5 }, + { 275000000, P_PLL18, 2, 0, 0 }, + { 550000000, P_PLL18, 1, 0, 0 }, +@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss + { } + }; + ++static const struct freq_tbl clk_tbl_nss_ipq8065[] = { ++ { 110000000, P_PLL18, 1, 1, 5 }, ++ { 275000000, P_PLL18, 2, 0, 0 }, ++ { 600000000, P_PLL18, 1, 0, 0 }, ++ { 800000000, P_PLL18, 1, 0, 0 }, ++ { } ++}; ++ + static struct clk_dyn_rcg ubi32_core1_src_clk = { + .ns_reg[0] = 0x3d2c, + .ns_reg[1] = 0x3d30, +@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr + .pre_div_width = 2, + }, + .mux_sel_bit = 0, +- .freq_tbl = clk_tbl_nss, ++ /* nss freq table is selected based on the SoC compatible */ + .clkr = { + .enable_reg = 0x3d20, + .enable_mask = BIT(1), +@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr + .pre_div_width = 2, + }, + .mux_sel_bit = 0, +- .freq_tbl = clk_tbl_nss, ++ /* nss freq table is selected based on the SoC compatible */ + .clkr = { + .enable_reg = 0x3d40, + .enable_mask = BIT(1), +@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat + if (ret) + return ret; + ++ if (of_machine_is_compatible("qcom,ipq8065")) { ++ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; ++ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; ++ } else { ++ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064; ++ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064; ++ } ++ + ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); + if (ret) + return ret; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch new file mode 100644 index 0000000000..3d55cb421a --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-08-linux-next-clk-qcom-gcc-ipq806x-add-unusued-flag-for-critical-c.patch @@ -0,0 +1,65 @@ +From 28aa450d38e521de45be951df052d2c49a17fae2 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:28 +0100 +Subject: [PATCH 08/14] clk: qcom: gcc-ipq806x: add unusued flag for critical + clock + +Some clocks are used by other devices present on the SoC. For example +the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to +reject any regulator change command. These clock should never be +disabled. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, +- .flags = CLK_SET_PARENT_GATE, ++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = + }, + .num_parents = 1, + .ops = &clk_branch_ops, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), + .ops = &clk_rcg_ops, +- .flags = CLK_SET_PARENT_GATE, ++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = + }, + .num_parents = 1, + .ops = &clk_branch_ops, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_h_clk", + .ops = &clk_branch_ops, ++ .flags = CLK_IGNORE_UNUSED, + }, + }, + }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch new file mode 100644 index 0000000000..22bd040d1b --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-09-linux-next-clk-qcom-clk-rcg-add-clk_rcg_floor_ops-ops.patch @@ -0,0 +1,69 @@ +From 33958ad3fc02aeb06a4634e59689a9559d968e1f Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:29 +0100 +Subject: [PATCH 09/14] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops + +Add clk_rcg_floor_ops for clock that can't provide a stable freq and +require to use a floor freq to provide the requested frequency. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com +--- + drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++ + drivers/clk/qcom/clk-rcg.h | 1 + + 2 files changed, 25 insertions(+) + +--- a/drivers/clk/qcom/clk-rcg.c ++++ b/drivers/clk/qcom/clk-rcg.c +@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_h + return __clk_rcg_set_rate(rcg, f); + } + ++static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_rcg *rcg = to_clk_rcg(hw); ++ const struct freq_tbl *f; ++ ++ f = qcom_find_freq_floor(rcg->freq_tbl, rate); ++ if (!f) ++ return -EINVAL; ++ ++ return __clk_rcg_set_rate(rcg, f); ++} ++ + static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = { + }; + EXPORT_SYMBOL_GPL(clk_rcg_ops); + ++const struct clk_ops clk_rcg_floor_ops = { ++ .enable = clk_enable_regmap, ++ .disable = clk_disable_regmap, ++ .get_parent = clk_rcg_get_parent, ++ .set_parent = clk_rcg_set_parent, ++ .recalc_rate = clk_rcg_recalc_rate, ++ .determine_rate = clk_rcg_determine_rate, ++ .set_rate = clk_rcg_set_floor_rate, ++}; ++EXPORT_SYMBOL_GPL(clk_rcg_floor_ops); ++ + const struct clk_ops clk_rcg_bypass_ops = { + .enable = clk_enable_regmap, + .disable = clk_disable_regmap, +--- a/drivers/clk/qcom/clk-rcg.h ++++ b/drivers/clk/qcom/clk-rcg.h +@@ -86,6 +86,7 @@ struct clk_rcg { + }; + + extern const struct clk_ops clk_rcg_ops; ++extern const struct clk_ops clk_rcg_floor_ops; + extern const struct clk_ops clk_rcg_bypass_ops; + extern const struct clk_ops clk_rcg_bypass2_ops; + extern const struct clk_ops clk_rcg_pixel_ops; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch new file mode 100644 index 0000000000..3bb5e57c87 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-10-linux-next-clk-qcom-gcc-ipq806x-add-additional-freq-for-sdc-tab.patch @@ -0,0 +1,38 @@ +From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:30 +0100 +Subject: [PATCH 10/14] clk: qcom: gcc-ipq806x: add additional freq for sdc + table + +Add additional freq supported for the sdc table. The ops are changed to +the floor_ops to handle a freq request of 52kHz where we need to provide +a freq of 51.2kHz instead for stability reason. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc + { 20210000, P_PLL8, 1, 1, 19 }, + { 24000000, P_PLL8, 4, 1, 4 }, + { 48000000, P_PLL8, 4, 1, 2 }, ++ { 51200000, P_PLL8, 1, 2, 15 }, + { 64000000, P_PLL8, 3, 1, 2 }, + { 96000000, P_PLL8, 4, 0, 0 }, + { 192000000, P_PLL8, 2, 0, 0 }, +@@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = { + .name = "sdc1_src", + .parent_data = gcc_pxo_pll8, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), +- .ops = &clk_rcg_ops, ++ .ops = &clk_rcg_floor_ops, + }, + } + }; diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch new file mode 100644 index 0000000000..858c6f78a5 --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-11-linux-next-dt-bindings-clock-add-ipq8064-ce5-clk-define.patch @@ -0,0 +1,39 @@ +From b565d66403e3df303a058c0d8d00d0fc6aeb2ddc Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:31 +0100 +Subject: [PATCH 11/14] dt-bindings: clock: add ipq8064 ce5 clk define + +Add ipq8064 ce5 clk define needed for CryptoEngine in gcc driver. +Define CE5_SRC is not used so it's OK to change and we align it to +the QSDK naming. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Acked-by: Rob Herring <robh@kernel.org> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-12-ansuelsmth@gmail.com +--- + include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h +@@ -240,7 +240,7 @@ + #define PLL14 232 + #define PLL14_VOTE 233 + #define PLL18 234 +-#define CE5_SRC 235 ++#define CE5_A_CLK 235 + #define CE5_H_CLK 236 + #define CE5_CORE_CLK 237 + #define CE3_SLEEP_CLK 238 +@@ -283,5 +283,8 @@ + #define EBI2_AON_CLK 281 + #define NSSTCM_CLK_SRC 282 + #define NSSTCM_CLK 283 ++#define CE5_A_CLK_SRC 285 ++#define CE5_H_CLK_SRC 286 ++#define CE5_CORE_CLK_SRC 287 + + #endif diff --git a/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch index d1e047cabf..3ded707bf0 100644 --- a/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-12-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-clocks.patch @@ -1,31 +1,22 @@ -From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001 +From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001 From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Sun, 7 Feb 2021 17:23:38 +0100 -Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine +Date: Sat, 26 Feb 2022 14:52:32 +0100 +Subject: [PATCH 12/14] clk: qcom: gcc-ipq806x: add CryptoEngine clocks -Add missing clk and reset needed for nss additional core and crypto -engine. +Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com --- - drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++ - include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +- - include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 + - 3 files changed, 259 insertions(+), 1 deletion(-) + drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++ + 1 file changed, 244 insertions(+) --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = { - - static struct pll_freq_tbl pll18_freq_tbl[] = { - NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), -+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), - NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), -+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), - }; - - static struct clk_pll pll18 = { -@@ -245,6 +247,22 @@ static struct clk_pll pll18 = { +@@ -256,6 +256,24 @@ static struct clk_pll pll18 = { }, }; @@ -39,7 +30,9 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", -+ .parent_names = (const char *[]){ "pxo" }, ++ .parent_data = &(const struct clk_parent_data){ ++ .fw_name = "pxo", ++ }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, @@ -48,7 +41,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> enum { P_PXO, P_PLL8, -@@ -253,6 +271,7 @@ enum { +@@ -264,6 +282,7 @@ enum { P_CXO, P_PLL14, P_PLL18, @@ -56,8 +49,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> }; static const struct parent_map gcc_pxo_pll8_map[] = { -@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p - "pll18", +@@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_ + { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { @@ -69,13 +62,14 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + { P_PLL11, 3 }, +}; + -+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { -+ "pxo", -+ "pll8_vote", -+ "pll0_vote", -+ "pll14", -+ "pll18", -+ "pll11" ++static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { ++ { .fw_name = "pxo" }, ++ { .hw = &pll8_vote.hw }, ++ { .hw = &pll0_vote.hw }, ++ { .hw = &pll14.clkr.hw }, ++ { .hw = &pll18.clkr.hw }, ++ { .hw = &pll11.clkr.hw }, ++ +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { @@ -87,37 +81,20 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + { P_PLL11, 3 }, +}; + -+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { -+ "pxo", -+ "pll3", -+ "pll0_vote", -+ "pll14", -+ "pll18", -+ "pll11" ++static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { ++ { .fw_name = "pxo" }, ++ { .hw = &pll3.clkr.hw }, ++ { .hw = &pll0_vote.hw }, ++ { .hw = &pll14.clkr.hw }, ++ { .hw = &pll18.clkr.hw }, ++ { .hw = &pll11.clkr.hw }, ++ +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, -@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc - { 20210000, P_PLL8, 1, 1, 19 }, - { 24000000, P_PLL8, 4, 1, 4 }, - { 48000000, P_PLL8, 4, 1, 2 }, -+ { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ - { 64000000, P_PLL8, 3, 1, 2 }, - { 96000000, P_PLL8, 4, 0, 0 }, - { 192000000, P_PLL8, 2, 0, 0 }, -@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss - { 110000000, P_PLL18, 1, 1, 5 }, - { 275000000, P_PLL18, 2, 0, 0 }, - { 550000000, P_PLL18, 1, 0, 0 }, -+ { 600000000, P_PLL18, 1, 0, 0 }, - { 733000000, P_PLL18, 1, 0, 0 }, -+ { 800000000, P_PLL18, 1, 0, 0 }, - { } - }; - -@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr +@@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_sr }, }; @@ -154,8 +131,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", -+ .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11, -+ .num_parents = 6, ++ .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, @@ -171,8 +148,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", -+ .parent_names = (const char *[]){ -+ "ce5_core_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, @@ -214,8 +191,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", -+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = 6, ++ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, @@ -231,8 +208,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", -+ .parent_names = (const char *[]){ -+ "ce5_a_clk_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, @@ -274,8 +251,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", -+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = 6, ++ .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, ++ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, @@ -291,8 +268,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", -+ .parent_names = (const char *[]){ -+ "ce5_h_clk_src", ++ .parent_hws = (const struct clk_hw*[]){ ++ &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, @@ -304,7 +281,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, -@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, @@ -312,7 +289,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, -@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, @@ -325,48 +302,3 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i - [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, - [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, - [GMAC_AHB_RESET] = { 0x3e24, 0 }, -+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, -+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, -+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, -+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, -+ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, - [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, - [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, - [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, ---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h -@@ -240,7 +240,7 @@ - #define PLL14 232 - #define PLL14_VOTE 233 - #define PLL18 234 --#define CE5_SRC 235 -+#define CE5_A_CLK 235 - #define CE5_H_CLK 236 - #define CE5_CORE_CLK 237 - #define CE3_SLEEP_CLK 238 -@@ -283,5 +283,8 @@ - #define EBI2_AON_CLK 281 - #define NSSTCM_CLK_SRC 282 - #define NSSTCM_CLK 283 -+#define CE5_A_CLK_SRC 285 -+#define CE5_H_CLK_SRC 286 -+#define CE5_CORE_CLK_SRC 287 - - #endif ---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h -@@ -163,5 +163,10 @@ - #define NSS_CAL_PRBS_RST_N_RESET 154 - #define NSS_LCKDT_RST_N_RESET 155 - #define NSS_SRDS_N_RESET 156 -+#define CRYPTO_ENG1_RESET 157 -+#define CRYPTO_ENG2_RESET 158 -+#define CRYPTO_ENG3_RESET 159 -+#define CRYPTO_ENG4_RESET 160 -+#define CRYPTO_AHB_RESET 161 - - #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch new file mode 100644 index 0000000000..5d05c2b3af --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-13-linux-next-dt-bindings-reset-add-ipq8064-ce5-resets.patch @@ -0,0 +1,29 @@ +From f4a7e56f4956f0450b9f671ed93d45ffcc15aa62 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Tue, 18 Jan 2022 01:22:05 +0100 +Subject: [PATCH v6 13/15] dt-bindings: reset: add ipq8064 ce5 resets + +Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Acked-by: Philipp Zabel <p.zabel@pengutronix.de> +Acked-by: Rob Herring <robh@kernel.org> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +--- + include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h +@@ -163,5 +163,10 @@ + #define NSS_CAL_PRBS_RST_N_RESET 154 + #define NSS_LCKDT_RST_N_RESET 155 + #define NSS_SRDS_N_RESET 156 ++#define CRYPTO_ENG1_RESET 157 ++#define CRYPTO_ENG2_RESET 158 ++#define CRYPTO_ENG3_RESET 159 ++#define CRYPTO_ENG4_RESET 160 ++#define CRYPTO_AHB_RESET 161 + + #endif diff --git a/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch b/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch new file mode 100644 index 0000000000..a26f67e36e --- /dev/null +++ b/target/linux/ipq806x/patches-5.15/100-v5.18-14-linux-next-clk-qcom-gcc-ipq806x-add-CryptoEngine-resets.patch @@ -0,0 +1,30 @@ +From 4f865bdcb44fb18951de94be5c2ec37a891a8d03 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Sat, 26 Feb 2022 14:52:34 +0100 +Subject: [PATCH 14/14] clk: qcom: gcc-ipq806x: add CryptoEngine resets + +Add missing CryptoEngine resets. + +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Reviewed-by: Stephen Boyd <sboyd@kernel.org> +Tested-by: Jonathan McDowell <noodles@earth.li> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com +--- + drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -3320,6 +3320,11 @@ static const struct qcom_reset_map gcc_i + [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, + [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, + [GMAC_AHB_RESET] = { 0x3e24, 0 }, ++ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, ++ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, ++ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, ++ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, ++ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, + [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, + [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, + [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, |