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authorAnsuel Smith <ansuelsmth@gmail.com>2021-04-08 16:20:36 +0200
committerPetr Štetiar <ynezz@true.cz>2021-05-07 07:05:16 +0200
commit6e411b8416388a9c8be1b2291be9b5adeeb07784 (patch)
tree759ff5d9c5f718aa8cf211b0f7ae3f697b4c3ed6 /target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
parent5dbbefcbccc06cbcc8da0706afba52f741781d47 (diff)
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ipq806x: backport cpufreq changes to 5.4
The new cpufreq driver requires different dts bindings. Backport the new driver to kernel 5.4 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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diff --git a/target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch b/target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
new file mode 100644
index 0000000000..316e18b790
--- /dev/null
+++ b/target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
@@ -0,0 +1,237 @@
+From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Sat, 22 Feb 2020 18:02:17 +0100
+Subject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings
+
+Document dedicated cpufreq for Krait CPUs.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+---
+ .../bindings/cpufreq/qcom-cpufreq-krait.yaml | 221 ++++++++++++++++++
+ 1 file changed, 221 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
+@@ -0,0 +1,221 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: CPU Frequency scaling driver for Krait SoCs
++
++maintainers:
++ - Ansuel Smith <ansuelsmth@gmail.com>
++
++description: |
++ The krait cpufreq driver is a dedicated frequency scaling driver
++ based on cpufreq-dt generic driver that scale L2 cache and the
++ cores. TEST
++
++ The L2 cache is scaled based on the max clk across all cores and
++ the clock is decided based on the opp-level set in the device tree.
++
++ Different core freq can be linked to a specific l2 freq and the driver
++ on frequency change will scale the core and the l2 clk based of the
++ linked freq.
++
++ On Krait SoC is present a bug and on every L2 clk change the driver
++ needs to set the clk to the idle freq before changing it to the new value.
++
++ This requires the qcom cpufreq nvmem driver to parse the different opp
++ core clk and an additional opp table for the l2 scaling.
++
++ If the driver detect broken config (for example missing opp-level) the
++ cpufreq driver skips the l2 scaling
++
++ Referring to this example opp-level can be used to link a range of cpu freq
++ to a specific l2 freq:
++ cpu opp freq 384000000 has opp-level 0
++ l2 opp freq 384000000 has opp-level 0
++ The driver will scale l2 to 384000000
++
++ cpu opp freq 600000000-1000000000 has opp-level 1
++ l2 opp freq 1000000000 has opp-level 1
++ The driver will scale l2 to 1000000000
++
++allOf:
++ - $ref: /schemas/cache-controller.yaml#
++
++select:
++ properties:
++ compatible:
++ items:
++ - enum:
++ - qcom,krait-cache
++
++ required:
++ - compatible
++
++properties:
++ compatible:
++ items:
++ - const: qcom,krait-cache
++ - const: cache
++
++ cache-level:
++ const: 2
++
++ clocks:
++ maxItems: 1
++
++ clock-names:
++ const: l2
++
++ l2-supply: true
++
++ operating-points-v2: true
++
++required:
++ - compatible
++ - cache-level
++ - clocks
++ - clock-names
++ - l2-supply
++ - operating-points-v2
++
++additionalProperties: false
++
++examples:
++ - |
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ compatible = "qcom,krait";
++ enable-method = "qcom,kpss-acc-v1";
++ device_type = "cpu";
++ reg = <0>;
++ next-level-cache = <&L2>;
++ qcom,acc = <&acc0>;
++ qcom,saw = <&saw0>;
++ clocks = <&kraitcc 0>, <&kraitcc 4>;
++ clock-names = "cpu", "l2";
++ clock-latency = <100000>;
++ cpu-supply = <&smb208_s2a>;
++ operating-points-v2 = <&opp_table0>;
++ voltage-tolerance = <5>;
++ cooling-min-state = <0>;
++ cooling-max-state = <10>;
++ #cooling-cells = <2>;
++ cpu-idle-states = <&CPU_SPC>;
++ };
++
++ /* ... */
++
++ };
++
++ opp_table0: opp_table0 {
++ compatible = "operating-points-v2-kryo-cpu";
++ nvmem-cells = <&speedbin_efuse>;
++
++ opp-384000000 {
++ opp-hz = /bits/ 64 <384000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1000000>;
++ opp-microvolt-speed0-pvs1-v0 = <925000>;
++ opp-microvolt-speed0-pvs2-v0 = <875000>;
++ opp-microvolt-speed0-pvs3-v0 = <800000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <0>;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1050000>;
++ opp-microvolt-speed0-pvs1-v0 = <975000>;
++ opp-microvolt-speed0-pvs2-v0 = <925000>;
++ opp-microvolt-speed0-pvs3-v0 = <850000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-800000000 {
++ opp-hz = /bits/ 64 <800000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1100000>;
++ opp-microvolt-speed0-pvs1-v0 = <1025000>;
++ opp-microvolt-speed0-pvs2-v0 = <995000>;
++ opp-microvolt-speed0-pvs3-v0 = <900000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-1000000000 {
++ opp-hz = /bits/ 64 <1000000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1150000>;
++ opp-microvolt-speed0-pvs1-v0 = <1075000>;
++ opp-microvolt-speed0-pvs2-v0 = <1025000>;
++ opp-microvolt-speed0-pvs3-v0 = <950000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1200000>;
++ opp-microvolt-speed0-pvs1-v0 = <1125000>;
++ opp-microvolt-speed0-pvs2-v0 = <1075000>;
++ opp-microvolt-speed0-pvs3-v0 = <1000000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <2>;
++ };
++
++ opp-1400000000 {
++ opp-hz = /bits/ 64 <1400000000>;
++ opp-microvolt-speed0-pvs0-v0 = <1250000>;
++ opp-microvolt-speed0-pvs1-v0 = <1175000>;
++ opp-microvolt-speed0-pvs2-v0 = <1125000>;
++ opp-microvolt-speed0-pvs3-v0 = <1050000>;
++ opp-supported-hw = <0x1>;
++ clock-latency-ns = <100000>;
++ opp-level = <2>;
++ };
++ };
++
++ opp_table_l2: opp_table_l2 {
++ compatible = "operating-points-v2";
++
++ opp-384000000 {
++ opp-hz = /bits/ 64 <384000000>;
++ opp-microvolt = <1100000>;
++ clock-latency-ns = <100000>;
++ opp-level = <0>;
++ };
++ opp-1000000000 {
++ opp-hz = /bits/ 64 <1000000000>;
++ opp-microvolt = <1100000>;
++ clock-latency-ns = <100000>;
++ opp-level = <1>;
++ };
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt = <1150000>;
++ clock-latency-ns = <100000>;
++ opp-level = <2>;
++ };
++ };
++
++ soc {
++ L2: l2-cache {
++ compatible = "qcom,krait-cache", "cache";
++ cache-level = <2>;
++
++ clocks = <&kraitcc 4>;
++ clock-names = "l2";
++ l2-supply = <&smb208_s1a>;
++ operating-points-v2 = <&opp_table_l2>;
++ };
++ };
++
++...