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| author | Ansuel Smith <ansuelsmth@gmail.com> | 2021-03-01 00:58:57 +0100 |
|---|---|---|
| committer | Petr Štetiar <ynezz@true.cz> | 2021-05-07 07:05:16 +0200 |
| commit | d53be2a2e98129ecf32009893ec46b1ce644721a (patch) | |
| tree | a501ae76b98989a5c6b16762c185212c081b840b /target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch | |
| parent | 861b82d36ae43efec8d16e61b82482e38996af92 (diff) | |
| download | upstream-d53be2a2e98129ecf32009893ec46b1ce644721a.tar.gz upstream-d53be2a2e98129ecf32009893ec46b1ce644721a.tar.bz2 upstream-d53be2a2e98129ecf32009893ec46b1ce644721a.zip | |
ipq806x: copy kernel 5.4 patches to 5.10
Copy kernel 5.4 patches and config to 5.10
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Diffstat (limited to 'target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch b/target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch new file mode 100644 index 0000000000..f75f994904 --- /dev/null +++ b/target/linux/ipq806x/patches-5.10/851-add-gsbi1-dts.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -865,6 +865,41 @@ + reg = <0x12100000 0x10000>; + }; + ++ gsbi1: gsbi@12440000 { ++ compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <1>; ++ reg = <0x12440000 0x100>; ++ clocks = <&gcc GSBI1_H_CLK>; ++ clock-names = "iface"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ status = "disabled"; ++ ++ syscon-tcsr = <&tcsr>; ++ ++ gsbi1_serial: serial@12450000 { ++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; ++ reg = <0x12450000 0x100>, ++ <0x12400000 0x03>; ++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ gsbi1_i2c: i2c@12460000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x12460000 0x1000>; ++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; ++ clock-names = "core", "iface"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; |