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author | Christian Lamparter <chunkeey@gmail.com> | 2019-02-26 16:22:27 +0100 |
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committer | Christian Lamparter <chunkeey@gmail.com> | 2019-02-28 11:26:11 +0100 |
commit | 18e942b6c4e51a5a717a121697a63f3f98d93b19 (patch) | |
tree | b1370bdf6417475abba7d2d3a722a7ca2d29738b /target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-qxwlan-e2600ac-c1.dts | |
parent | 46b949a067e5babcd9a554c84599a277ce13d822 (diff) | |
download | upstream-18e942b6c4e51a5a717a121697a63f3f98d93b19.tar.gz upstream-18e942b6c4e51a5a717a121697a63f3f98d93b19.tar.bz2 upstream-18e942b6c4e51a5a717a121697a63f3f98d93b19.zip |
ipq40xx: fix pcie msi IRQ trigger level
From: Niklas Cassel <niklas.cassel@linaro.org>
|The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level
|triggered interrupt.
|
|The msi_ctrl_int will be high for as long as any MSI status bit is set,
|thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the
|IRQ handler to keep getting called, as long as any MSI status bit is set.
|[...]
|Not having the correct IRQ type defined will cause us to lose interrupts,
|which in turn causes timeouts in the PCIe endpoint drivers.
|
|Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
|Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Diffstat (limited to 'target/linux/ipq40xx/files-4.14/arch/arm/boot/dts/qcom-ipq4019-qxwlan-e2600ac-c1.dts')
0 files changed, 0 insertions, 0 deletions