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| author | Stijn Segers <francesco.borromini@inventati.org> | 2017-05-24 22:39:28 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-05-24 22:47:01 +0200 |
| commit | 215c1d05b8bb7b99cc8c40a877f649c5b1c15198 (patch) | |
| tree | e44256447d81a6ca36a1c616689494b12a83bce4 /target/linux/generic/patches-4.4/062-03-MIPS-Only-change-28-to-thread_info-if-coming-from-us.patch | |
| parent | d1a0fc3ec8e5323e95bec8db581bc7758aed783f (diff) | |
| download | upstream-215c1d05b8bb7b99cc8c40a877f649c5b1c15198.tar.gz upstream-215c1d05b8bb7b99cc8c40a877f649c5b1c15198.tar.bz2 upstream-215c1d05b8bb7b99cc8c40a877f649c5b1c15198.zip | |
kernel: update kernel 4.4 to 4.4.69
Bump the 17.01 tree kernel to 4.4.69. Trunk 4.4 and 17.01 4.4 have diverged, talked this
through with jow, he was okay with a clean diff against 17.01 and not a backported trunk
patch.
The following patches were applied upstream:
* 062-[1-6]-MIPS-* series
* 042-0004-mtd-bcm47xxpart-fix-parsing-first-block
Reintroduced lantiq/patches-4.4/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup, as
it was incorrectly included upstream thus dropped from LEDE, but subsequently
reverted upstream. Thanks to Kevin Darbyshire-Bryant for pointing me to it.
Compile-tested on: ar71xx, ramips/mt7621, x86/64.
Run-tested on: ar71xx, ramips/mt7621, x86/64.
Signed-off-by: Stijn Segers <francesco.borromini@inventati.org>
Diffstat (limited to 'target/linux/generic/patches-4.4/062-03-MIPS-Only-change-28-to-thread_info-if-coming-from-us.patch')
| -rw-r--r-- | target/linux/generic/patches-4.4/062-03-MIPS-Only-change-28-to-thread_info-if-coming-from-us.patch | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/target/linux/generic/patches-4.4/062-03-MIPS-Only-change-28-to-thread_info-if-coming-from-us.patch b/target/linux/generic/patches-4.4/062-03-MIPS-Only-change-28-to-thread_info-if-coming-from-us.patch deleted file mode 100644 index e13c67be60..0000000000 --- a/target/linux/generic/patches-4.4/062-03-MIPS-Only-change-28-to-thread_info-if-coming-from-us.patch +++ /dev/null @@ -1,48 +0,0 @@ -From: Matt Redfearn <matt.redfearn@imgtec.com> -Date: Mon, 19 Dec 2016 14:20:58 +0000 -Subject: [PATCH] MIPS: Only change $28 to thread_info if coming from user - mode - -The SAVE_SOME macro is used to save the execution context on all -exceptions. -If an exception occurs while executing user code, the stack is switched -to the kernel's stack for the current task, and register $28 is switched -to point to the current_thread_info, which is at the bottom of the stack -region. -If the exception occurs while executing kernel code, the stack is left, -and this change ensures that register $28 is not updated. This is the -correct behaviour when the kernel can be executing on the separate irq -stack, because the thread_info will not be at the base of it. - -With this change, register $28 is only switched to it's kernel -conventional usage of the currrent thread info pointer at the point at -which execution enters kernel space. Doing it on every exception was -redundant, but OK without an IRQ stack, but will be erroneous once that -is introduced. - -Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> -Reviewed-by: Maciej W. Rozycki <macro@imgtec.com> ---- - ---- a/arch/mips/include/asm/stackframe.h -+++ b/arch/mips/include/asm/stackframe.h -@@ -216,12 +216,19 @@ - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) -+ -+ /* Set thread_info if we're coming from user mode */ -+ mfc0 k0, CP0_STATUS -+ sll k0, 3 /* extract cu0 bit */ -+ bltz k0, 9f -+ - ori $28, sp, _THREAD_MASK - xori $28, _THREAD_MASK - #ifdef CONFIG_CPU_CAVIUM_OCTEON - .set mips64 - pref 0, 0($28) /* Prefetch the current pointer */ - #endif -+9: - .set pop - .endm - |