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authorHauke Mehrtens <hauke@hauke-m.de>2013-01-10 14:05:18 +0000
committerHauke Mehrtens <hauke@hauke-m.de>2013-01-10 14:05:18 +0000
commit885eea184225e2d190f7aa8742ac806034caa9fc (patch)
treed60d951609d8e3a315c92b06a0670dc814525594 /target/linux/generic/patches-3.3
parenta2950fabd4c84c867bf303e2e92bf99c2eb8b87a (diff)
downloadupstream-885eea184225e2d190f7aa8742ac806034caa9fc.tar.gz
upstream-885eea184225e2d190f7aa8742ac806034caa9fc.tar.bz2
upstream-885eea184225e2d190f7aa8742ac806034caa9fc.zip
kernel: update bcma and ssb to master-2013-01-09 from wireless-testing
SVN-Revision: 35080
Diffstat (limited to 'target/linux/generic/patches-3.3')
-rw-r--r--target/linux/generic/patches-3.3/020-ssb_update.patch583
-rw-r--r--target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch22
-rw-r--r--target/linux/generic/patches-3.3/025-bcma_backport.patch588
3 files changed, 1041 insertions, 152 deletions
diff --git a/target/linux/generic/patches-3.3/020-ssb_update.patch b/target/linux/generic/patches-3.3/020-ssb_update.patch
index bfcb556b03..3a3afd020e 100644
--- a/target/linux/generic/patches-3.3/020-ssb_update.patch
+++ b/target/linux/generic/patches-3.3/020-ssb_update.patch
@@ -1,3 +1,75 @@
+--- a/arch/mips/bcm47xx/nvram.c
++++ b/arch/mips/bcm47xx/nvram.c
+@@ -43,8 +43,8 @@ static void early_nvram_init(void)
+ #ifdef CONFIG_BCM47XX_SSB
+ case BCM47XX_BUS_TYPE_SSB:
+ mcore_ssb = &bcm47xx_bus.ssb.mipscore;
+- base = mcore_ssb->flash_window;
+- lim = mcore_ssb->flash_window_size;
++ base = mcore_ssb->pflash.window;
++ lim = mcore_ssb->pflash.window_size;
+ break;
+ #endif
+ #ifdef CONFIG_BCM47XX_BCMA
+--- a/arch/mips/bcm47xx/wgt634u.c
++++ b/arch/mips/bcm47xx/wgt634u.c
+@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
+ SSB_CHIPCO_IRQ_GPIO);
+ }
+
+- wgt634u_flash_data.width = mcore->flash_buswidth;
+- wgt634u_flash_resource.start = mcore->flash_window;
+- wgt634u_flash_resource.end = mcore->flash_window
+- + mcore->flash_window_size
++ wgt634u_flash_data.width = mcore->pflash.buswidth;
++ wgt634u_flash_resource.start = mcore->pflash.window;
++ wgt634u_flash_resource.end = mcore->pflash.window
++ + mcore->pflash.window_size
+ - 1;
+ return platform_add_devices(wgt634u_devices,
+ ARRAY_SIZE(wgt634u_devices));
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
+
+ If unsure, say N
+
++config SSB_SFLASH
++ bool "SSB serial flash support"
++ depends on SSB_DRIVER_MIPS && BROKEN
++ default y
++
+ # Assumption: We are on embedded, if we compile the MIPS core.
+ config SSB_EMBEDDED
+ bool
+@@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
+
+ If unsure, say N
+
++config SSB_DRIVER_GPIO
++ bool "SSB GPIO driver"
++ depends on SSB && GPIOLIB
++ help
++ Driver to provide access to the GPIO pins on the bus.
++
++ If unsure, say N
++
+ endmenu
+--- a/drivers/ssb/Makefile
++++ b/drivers/ssb/Makefile
+@@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
+ # built-in drivers
+ ssb-y += driver_chipcommon.o
+ ssb-y += driver_chipcommon_pmu.o
++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
+ ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
+ ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
+ ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
+ ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
++ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
+
+ # b43 pci-ssb-bridge driver
+ # Not strictly a part of SSB, but kept here for convenience
--- a/drivers/ssb/b43_pci_bridge.c
+++ b/drivers/ssb/b43_pci_bridge.c
@@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
@@ -34,7 +106,7 @@
#include "ssb_private.h"
-@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
+@@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
cc->fast_pwrup_delay = tmp;
}
@@ -104,7 +176,14 @@
void ssb_chipcommon_init(struct ssb_chipcommon *cc)
{
if (!cc->dev)
-@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
+ return; /* We don't have a ChipCommon */
++
++ spin_lock_init(&cc->gpio_lock);
++
+ if (cc->dev->id.revision >= 11)
+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
+@@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
chipco_powercontrol_init(cc);
ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
calc_fast_powerup_delay(cc);
@@ -116,7 +195,7 @@
}
void ssb_chipco_suspend(struct ssb_chipcommon *cc)
-@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
+@@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
}
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
@@ -147,7 +226,106 @@
}
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
-@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
+@@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
+
+ u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+ EXPORT_SYMBOL(ssb_chipco_gpio_control);
+
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
+ {
+- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
++}
++
++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
++{
++ unsigned long flags;
++ u32 res = 0;
++
++ if (cc->dev->id.revision < 20)
++ return 0xffffffff;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
++}
++
++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
++{
++ unsigned long flags;
++ u32 res = 0;
++
++ if (cc->dev->id.revision < 20)
++ return 0xffffffff;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ #ifdef CONFIG_SSB_SERIAL
+@@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
chipco_read32(cc, SSB_CHIPCO_CORECTL)
| SSB_CHIPCO_CORECTL_UARTCLK0);
} else if ((ccrev >= 11) && (ccrev != 15)) {
@@ -288,9 +466,30 @@
+ return 0;
+ }
+}
+--- /dev/null
++++ b/drivers/ssb/driver_chipcommon_sflash.c
+@@ -0,0 +1,18 @@
++/*
++ * Sonics Silicon Backplane
++ * ChipCommon serial flash interface
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/ssb/ssb.h>
++
++#include "ssb_private.h"
++
++/* Initialize serial flash access */
++int ssb_sflash_init(struct ssb_chipcommon *cc)
++{
++ pr_err("Serial flash support is not implemented yet!\n");
++
++ return -ENOTSUPP;
++}
--- a/drivers/ssb/driver_extif.c
+++ b/drivers/ssb/driver_extif.c
-@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
+@@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
}
@@ -320,9 +519,250 @@
extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
+
+ return ticks;
++}
++
++void ssb_extif_init(struct ssb_extif *extif)
++{
++ if (!extif->dev)
++ return; /* We don't have a Extif core */
++ spin_lock_init(&extif->gpio_lock);
}
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
+@@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
+
+ u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
+ mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
+ mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
+ {
+- return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
++ unsigned long flags;
++ u32 res = 0;
++
++ spin_lock_irqsave(&extif->gpio_lock, flags);
++ res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
++ spin_unlock_irqrestore(&extif->gpio_lock, flags);
++
++ return res;
+ }
+--- /dev/null
++++ b/drivers/ssb/driver_gpio.c
+@@ -0,0 +1,176 @@
++/*
++ * Sonics Silicon Backplane
++ * GPIO driver
++ *
++ * Copyright 2011, Broadcom Corporation
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/gpio.h>
++#include <linux/export.h>
++#include <linux/ssb/ssb.h>
++
++#include "ssb_private.h"
++
++static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
++{
++ return container_of(chip, struct ssb_bus, gpio);
++}
++
++static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
++}
++
++static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
++}
++
++static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
++ unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
++ return 0;
++}
++
++static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
++ unsigned gpio, int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
++ ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
++ return 0;
++}
++
++static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
++ /* clear pulldown */
++ ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
++ /* Set pullup */
++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
++
++ return 0;
++}
++
++static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ /* clear pullup */
++ ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
++}
++
++static int ssb_gpio_chipco_init(struct ssb_bus *bus)
++{
++ struct gpio_chip *chip = &bus->gpio;
++
++ chip->label = "ssb_chipco_gpio";
++ chip->owner = THIS_MODULE;
++ chip->request = ssb_gpio_chipco_request;
++ chip->free = ssb_gpio_chipco_free;
++ chip->get = ssb_gpio_chipco_get_value;
++ chip->set = ssb_gpio_chipco_set_value;
++ chip->direction_input = ssb_gpio_chipco_direction_input;
++ chip->direction_output = ssb_gpio_chipco_direction_output;
++ chip->ngpio = 16;
++ /* There is just one SoC in one device and its GPIO addresses should be
++ * deterministic to address them more easily. The other buses could get
++ * a random base number. */
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ chip->base = 0;
++ else
++ chip->base = -1;
++
++ return gpiochip_add(chip);
++}
++
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++
++static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
++}
++
++static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
++}
++
++static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
++ unsigned gpio)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
++ return 0;
++}
++
++static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
++ unsigned gpio, int value)
++{
++ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++ ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
++ ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
++ return 0;
++}
++
++static int ssb_gpio_extif_init(struct ssb_bus *bus)
++{
++ struct gpio_chip *chip = &bus->gpio;
++
++ chip->label = "ssb_extif_gpio";
++ chip->owner = THIS_MODULE;
++ chip->get = ssb_gpio_extif_get_value;
++ chip->set = ssb_gpio_extif_set_value;
++ chip->direction_input = ssb_gpio_extif_direction_input;
++ chip->direction_output = ssb_gpio_extif_direction_output;
++ chip->ngpio = 5;
++ /* There is just one SoC in one device and its GPIO addresses should be
++ * deterministic to address them more easily. The other buses could get
++ * a random base number. */
++ if (bus->bustype == SSB_BUSTYPE_SSB)
++ chip->base = 0;
++ else
++ chip->base = -1;
++
++ return gpiochip_add(chip);
++}
++
++#else
++static int ssb_gpio_extif_init(struct ssb_bus *bus)
++{
++ return -ENOTSUPP;
++}
++#endif
++
++int ssb_gpio_init(struct ssb_bus *bus)
++{
++ if (ssb_chipco_available(&bus->chipco))
++ return ssb_gpio_chipco_init(bus);
++ else if (ssb_extif_available(&bus->extif))
++ return ssb_gpio_extif_init(bus);
++ else
++ SSB_WARN_ON(1);
++
++ return -1;
++}
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
@@ -337,7 +777,7 @@
mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
else
mcore->nr_serial_ports = 0;
-@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
+@@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct
{
struct ssb_bus *bus = mcore->dev->bus;
@@ -358,7 +798,8 @@
+ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
+ case SSB_CHIPCO_FLASHT_STSER:
+ case SSB_CHIPCO_FLASHT_ATSER:
-+ pr_err("Serial flash not supported\n");
++ pr_debug("Found serial flash\n");
++ ssb_sflash_init(&bus->chipco);
+ break;
+ case SSB_CHIPCO_FLASHT_PARA:
+ pr_debug("Found parallel flash\n");
@@ -378,7 +819,7 @@
}
}
-@@ -208,9 +224,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+@@ -208,9 +225,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
struct ssb_bus *bus = mcore->dev->bus;
u32 pll_type, n, m, rate = 0;
@@ -393,7 +834,7 @@
ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
} else
return 0;
-@@ -246,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
+@@ -246,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
hz = 100000000;
ns = 1000000000 / hz;
@@ -534,7 +975,22 @@
ssb_bus_may_powerdown(bus);
err = ssb_devices_register(bus);
-@@ -1094,6 +1086,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
+@@ -812,7 +804,14 @@ static int __devinit ssb_bus_register(st
+ if (err)
+ goto err_pcmcia_exit;
+ ssb_chipcommon_init(&bus->chipco);
++ ssb_extif_init(&bus->extif);
+ ssb_mipscore_init(&bus->mipscore);
++ err = ssb_gpio_init(bus);
++ if (err == -ENOTSUPP)
++ ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
++ else if (err)
++ ssb_dprintk(KERN_ERR PFX
++ "Error registering GPIO driver: %i\n", err);
+ err = ssb_fetch_invariants(bus, get_invariants);
+ if (err) {
+ ssb_bus_may_powerdown(bus);
+@@ -1094,6 +1093,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
u32 plltype;
u32 clkctl_n, clkctl_m;
@@ -544,7 +1000,7 @@
if (ssb_extif_available(&bus->extif))
ssb_extif_get_clockcontrol(&bus->extif, &plltype,
&clkctl_n, &clkctl_m);
-@@ -1131,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
+@@ -1131,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
case SSB_IDLOW_SSBREV_27: /* same here */
return SSB_TMSLOW_REJECT; /* this is a guess */
default:
@@ -890,7 +1346,7 @@
#define PFX "ssb: "
-@@ -207,4 +208,38 @@ static inline void b43_pci_ssb_bridge_ex
+@@ -207,4 +208,66 @@ static inline void b43_pci_ssb_bridge_ex
}
#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
@@ -903,6 +1359,17 @@
+ u32 ticks);
+extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
+
++/* driver_chipcommon_sflash.c */
++#ifdef CONFIG_SSB_SFLASH
++int ssb_sflash_init(struct ssb_chipcommon *cc);
++#else
++static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
++{
++ pr_err("Serial flash not supported\n");
++ return 0;
++}
++#endif /* CONFIG_SSB_SFLASH */
++
+#ifdef CONFIG_SSB_DRIVER_EXTIF
+extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
+extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
@@ -928,18 +1395,38 @@
+}
+#endif /* CONFIG_SSB_EMBEDDED */
+
++#ifdef CONFIG_SSB_DRIVER_EXTIF
++extern void ssb_extif_init(struct ssb_extif *extif);
++#else
++static inline void ssb_extif_init(struct ssb_extif *extif)
++{
++}
++#endif
++
++#ifdef CONFIG_SSB_DRIVER_GPIO
++extern int ssb_gpio_init(struct ssb_bus *bus);
++#else /* CONFIG_SSB_DRIVER_GPIO */
++static inline int ssb_gpio_init(struct ssb_bus *bus)
++{
++ return -ENOTSUPP;
++}
++#endif /* CONFIG_SSB_DRIVER_GPIO */
++
#endif /* LINUX_SSB_PRIVATE_H_ */
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
-@@ -8,6 +8,7 @@
+@@ -6,8 +6,10 @@
+ #include <linux/types.h>
+ #include <linux/spinlock.h>
#include <linux/pci.h>
++#include <linux/gpio.h>
#include <linux/mod_devicetable.h>
#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
#include <linux/ssb/ssb_regs.h>
-@@ -16,6 +17,12 @@ struct pcmcia_device;
+@@ -16,6 +18,12 @@ struct pcmcia_device;
struct ssb_bus;
struct ssb_driver;
@@ -952,7 +1439,7 @@
struct ssb_sprom {
u8 revision;
u8 il0mac[6]; /* MAC address for 802.11b/g */
-@@ -26,9 +33,12 @@ struct ssb_sprom {
+@@ -26,9 +34,12 @@ struct ssb_sprom {
u8 et0mdcport; /* MDIO for enet0 */
u8 et1mdcport; /* MDIO for enet1 */
u16 board_rev; /* Board revision number from SPROM. */
@@ -967,7 +1454,7 @@
u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
u16 pa0b0;
-@@ -47,10 +57,10 @@ struct ssb_sprom {
+@@ -47,10 +58,10 @@ struct ssb_sprom {
u8 gpio1; /* GPIO pin 1 */
u8 gpio2; /* GPIO pin 2 */
u8 gpio3; /* GPIO pin 3 */
@@ -982,7 +1469,7 @@
u8 itssi_a; /* Idle TSSI Target for A-PHY */
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
u8 tri2g; /* 2.4GHz TX isolation */
-@@ -61,8 +71,8 @@ struct ssb_sprom {
+@@ -61,8 +72,8 @@ struct ssb_sprom {
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
@@ -993,7 +1480,7 @@
u8 rssisav2g; /* 2GHz RSSI params */
u8 rssismc2g;
u8 rssismf2g;
-@@ -82,16 +92,13 @@ struct ssb_sprom {
+@@ -82,16 +93,13 @@ struct ssb_sprom {
u16 boardflags2_hi; /* Board flags (bits 48-63) */
/* TODO store board flags in a single u64 */
@@ -1013,7 +1500,7 @@
} antenna_gain;
struct {
-@@ -103,14 +110,85 @@ struct ssb_sprom {
+@@ -103,14 +111,85 @@ struct ssb_sprom {
} ghz5;
} fem;
@@ -1101,7 +1588,7 @@
};
-@@ -166,6 +244,7 @@ struct ssb_bus_ops {
+@@ -166,6 +245,7 @@ struct ssb_bus_ops {
#define SSB_DEV_MINI_MACPHY 0x823
#define SSB_DEV_ARM_1176 0x824
#define SSB_DEV_ARM_7TDMI 0x825
@@ -1109,14 +1596,18 @@
/* Vendor-ID values */
#define SSB_VENDOR_BROADCOM 0x4243
-@@ -354,6 +433,7 @@ struct ssb_bus {
+@@ -354,7 +434,11 @@ struct ssb_bus {
#ifdef CONFIG_SSB_EMBEDDED
/* Lock for GPIO register access. */
spinlock_t gpio_lock;
+ struct platform_device *watchdog;
#endif /* EMBEDDED */
++#ifdef CONFIG_SSB_DRIVER_GPIO
++ struct gpio_chip gpio;
++#endif /* DRIVER_GPIO */
/* Internal-only stuff follows. Do not touch. */
+ struct list_head list;
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -504,7 +504,9 @@
@@ -1130,16 +1621,18 @@
/* Status register bits for ST flashes */
#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
-@@ -589,6 +591,8 @@ struct ssb_chipcommon {
+@@ -588,7 +590,10 @@ struct ssb_chipcommon {
+ u32 status;
/* Fast Powerup Delay constant */
u16 fast_pwrup_delay;
++ spinlock_t gpio_lock;
struct ssb_chipcommon_pmu pmu;
+ u32 ticks_per_ms;
+ u32 max_timer_ms;
};
static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
-@@ -628,8 +632,7 @@ enum ssb_clkmode {
+@@ -628,8 +633,7 @@ enum ssb_clkmode {
extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
enum ssb_clkmode mode);
@@ -1149,9 +1642,18 @@
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+@@ -642,6 +646,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
+ u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
+ u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
+ u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
++u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
++u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
+
+ #ifdef CONFIG_SSB_SERIAL
+ extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
--- a/include/linux/ssb/ssb_driver_extif.h
+++ b/include/linux/ssb/ssb_driver_extif.h
-@@ -152,6 +152,9 @@
+@@ -152,12 +152,16 @@
/* watchdog */
#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
@@ -1161,7 +1663,14 @@
#ifdef CONFIG_SSB_DRIVER_EXTIF
-@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
+
+ struct ssb_extif {
+ struct ssb_device *dev;
++ spinlock_t gpio_lock;
+ };
+
+ static inline bool ssb_extif_available(struct ssb_extif *extif)
+@@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
extern void ssb_extif_timing_init(struct ssb_extif *extif,
unsigned long ns);
@@ -1171,7 +1680,7 @@
/* Extif GPIO pin access */
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
-@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
+@@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
}
static inline
@@ -1414,3 +1923,25 @@
/* Values for boardflags_lo read from SPROM */
#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
+--- /dev/null
++++ b/include/linux/bcm47xx_wdt.h
+@@ -0,0 +1,19 @@
++#ifndef LINUX_BCM47XX_WDT_H_
++#define LINUX_BCM47XX_WDT_H_
++
++#include <linux/types.h>
++
++
++struct bcm47xx_wdt {
++ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
++ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
++ u32 max_timer_ms;
++
++ void *driver_data;
++};
++
++static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
++{
++ return wdt->driver_data;
++}
++#endif /* LINUX_BCM47XX_WDT_H_ */
diff --git a/target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch b/target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch
deleted file mode 100644
index 18feeab0be..0000000000
--- a/target/linux/generic/patches-3.3/021-ssb_bcma_watchdog_header.patch
+++ /dev/null
@@ -1,22 +0,0 @@
---- /dev/null
-+++ b/include/linux/bcm47xx_wdt.h
-@@ -0,0 +1,19 @@
-+#ifndef LINUX_BCM47XX_WDT_H_
-+#define LINUX_BCM47XX_WDT_H_
-+
-+#include <linux/types.h>
-+
-+
-+struct bcm47xx_wdt {
-+ u32 (*timer_set)(struct bcm47xx_wdt *, u32);
-+ u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
-+ u32 max_timer_ms;
-+
-+ void *driver_data;
-+};
-+
-+static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
-+{
-+ return wdt->driver_data;
-+}
-+#endif /* LINUX_BCM47XX_WDT_H_ */
diff --git a/target/linux/generic/patches-3.3/025-bcma_backport.patch b/target/linux/generic/patches-3.3/025-bcma_backport.patch
index 282da42242..a00bec30e2 100644
--- a/target/linux/generic/patches-3.3/025-bcma_backport.patch
+++ b/target/linux/generic/patches-3.3/025-bcma_backport.patch
@@ -1,33 +1,3 @@
---- a/arch/mips/bcm47xx/nvram.c
-+++ b/arch/mips/bcm47xx/nvram.c
-@@ -43,8 +43,8 @@ static void early_nvram_init(void)
- #ifdef CONFIG_BCM47XX_SSB
- case BCM47XX_BUS_TYPE_SSB:
- mcore_ssb = &bcm47xx_bus.ssb.mipscore;
-- base = mcore_ssb->flash_window;
-- lim = mcore_ssb->flash_window_size;
-+ base = mcore_ssb->pflash.window;
-+ lim = mcore_ssb->pflash.window_size;
- break;
- #endif
- #ifdef CONFIG_BCM47XX_BCMA
---- a/arch/mips/bcm47xx/wgt634u.c
-+++ b/arch/mips/bcm47xx/wgt634u.c
-@@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
- SSB_CHIPCO_IRQ_GPIO);
- }
-
-- wgt634u_flash_data.width = mcore->flash_buswidth;
-- wgt634u_flash_resource.start = mcore->flash_window;
-- wgt634u_flash_resource.end = mcore->flash_window
-- + mcore->flash_window_size
-+ wgt634u_flash_data.width = mcore->pflash.buswidth;
-+ wgt634u_flash_resource.start = mcore->pflash.window;
-+ wgt634u_flash_resource.end = mcore->pflash.window
-+ + mcore->pflash.window_size
- - 1;
- return platform_add_devices(wgt634u_devices,
- ARRAY_SIZE(wgt634u_devices));
--- a/drivers/bcma/Kconfig
+++ b/drivers/bcma/Kconfig
@@ -29,7 +29,7 @@ config BCMA_HOST_PCI
@@ -39,7 +9,7 @@
help
PCI core hostmode operation (external PCI bus).
-@@ -46,6 +46,25 @@ config BCMA_DRIVER_MIPS
+@@ -46,6 +46,33 @@ config BCMA_DRIVER_MIPS
If unsure, say N
@@ -62,12 +32,20 @@
+
+ If unsure, say N
+
++config BCMA_DRIVER_GPIO
++ bool "BCMA GPIO driver"
++ depends on BCMA && GPIOLIB
++ help
++ Driver to provide access to the GPIO pins of the bcma bus.
++
++ If unsure, say N
++
config BCMA_DEBUG
bool "BCMA debugging"
depends on BCMA
--- a/drivers/bcma/Makefile
+++ b/drivers/bcma/Makefile
-@@ -1,8 +1,11 @@
+@@ -1,8 +1,12 @@
bcma-y += main.o scan.o core.o sprom.o
bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
+bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
@@ -76,6 +54,7 @@
bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
+bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
++bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
obj-$(CONFIG_BCMA) += bcma.o
@@ -102,7 +81,16 @@
void bcma_bus_unregister(struct bcma_bus *bus);
int __init bcma_bus_early_register(struct bcma_bus *bus,
struct bcma_device *core_cc,
-@@ -39,8 +48,32 @@ void bcma_chipco_serial_init(struct bcma
+@@ -22,6 +31,8 @@ int __init bcma_bus_early_register(struc
+ int bcma_bus_suspend(struct bcma_bus *bus);
+ int bcma_bus_resume(struct bcma_bus *bus);
+ #endif
++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit);
+
+ /* scan.c */
+ int bcma_bus_scan(struct bcma_bus *bus);
+@@ -39,8 +50,32 @@ void bcma_chipco_serial_init(struct bcma
#endif /* CONFIG_BCMA_DRIVER_MIPS */
/* driver_chipcommon_pmu.c */
@@ -137,7 +125,7 @@
#ifdef CONFIG_BCMA_HOST_PCI
/* host_pci.c */
-@@ -48,8 +81,14 @@ extern int __init bcma_host_pci_init(voi
+@@ -48,8 +83,24 @@ extern int __init bcma_host_pci_init(voi
extern void __exit bcma_host_pci_exit(void);
#endif /* CONFIG_BCMA_HOST_PCI */
@@ -152,6 +140,16 @@
+void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
++#ifdef CONFIG_BCMA_DRIVER_GPIO
++/* driver_gpio.c */
++int bcma_gpio_init(struct bcma_drv_cc *cc);
++#else
++static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
++{
++ return -ENOTSUPP;
++}
++#endif /* CONFIG_BCMA_DRIVER_GPIO */
++
#endif
--- a/drivers/bcma/core.c
+++ b/drivers/bcma/core.c
@@ -226,7 +224,7 @@
#include <linux/bcma/bcma.h>
static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
-@@ -22,12 +25,93 @@ static inline u32 bcma_cc_write32_masked
+@@ -22,20 +25,119 @@ static inline u32 bcma_cc_write32_masked
return value;
}
@@ -323,8 +321,11 @@
+ if (cc->early_setup_done)
return;
++ spin_lock_init(&cc->gpio_lock);
++
if (cc->core->id.rev >= 11)
-@@ -36,6 +120,22 @@ void bcma_core_chipcommon_init(struct bc
+ cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
+ cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
if (cc->core->id.rev >= 35)
cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
@@ -347,7 +348,7 @@
if (cc->core->id.rev >= 20) {
bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
-@@ -44,7 +144,7 @@ void bcma_core_chipcommon_init(struct bc
+@@ -44,7 +146,7 @@ void bcma_core_chipcommon_init(struct bc
if (cc->capabilities & BCMA_CC_CAP_PMU)
bcma_pmu_init(cc);
if (cc->capabilities & BCMA_CC_CAP_PCTL)
@@ -356,7 +357,7 @@
if (cc->core->id.rev >= 16) {
if (cc->core->bus->sprom.leddc_on_time &&
-@@ -56,15 +156,33 @@ void bcma_core_chipcommon_init(struct bc
+@@ -56,15 +158,33 @@ void bcma_core_chipcommon_init(struct bc
((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
}
@@ -393,7 +394,110 @@
}
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
-@@ -118,8 +236,7 @@ void bcma_chipco_serial_init(struct bcma
+@@ -84,28 +204,97 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
+
+ u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
+ {
+- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
++ unsigned long flags;
++ u32 res;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
+ {
+- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
++ unsigned long flags;
++ u32 res;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
++/*
++ * If the bit is set to 0, chipcommon controlls this GPIO,
++ * if the bit is set to 1, it is used by some part of the chip and not our code.
++ */
+ u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
+ {
+- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
++ unsigned long flags;
++ u32 res;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+ EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
+
+ u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
+ {
+- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
++ unsigned long flags;
++ u32 res;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
+ {
+- return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
++ unsigned long flags;
++ u32 res;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
++}
++
++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++ unsigned long flags;
++ u32 res;
++
++ if (cc->core->id.rev < 20)
++ return 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
++}
++
++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++ unsigned long flags;
++ u32 res;
++
++ if (cc->core->id.rev < 20)
++ return 0;
++
++ spin_lock_irqsave(&cc->gpio_lock, flags);
++ res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
++ spin_unlock_irqrestore(&cc->gpio_lock, flags);
++
++ return res;
+ }
+
+ #ifdef CONFIG_BCMA_DRIVER_MIPS
+@@ -118,8 +307,7 @@ void bcma_chipco_serial_init(struct bcma
struct bcma_serial_port *ports = cc->serial_ports;
if (ccrev >= 11 && ccrev != 15) {
@@ -403,7 +507,7 @@
if (ccrev >= 21) {
/* Turn off UART clock before switching clocksource. */
bcma_cc_write32(cc, BCMA_CC_CORECTL,
-@@ -137,8 +254,7 @@ void bcma_chipco_serial_init(struct bcma
+@@ -137,8 +325,7 @@ void bcma_chipco_serial_init(struct bcma
| BCMA_CC_CORECTL_UARTCLKEN);
}
} else {
@@ -472,7 +576,22 @@
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
-@@ -54,38 +55,19 @@ void bcma_chipco_regctl_maskset(struct b
+@@ -12,12 +13,13 @@
+ #include <linux/export.h>
+ #include <linux/bcma/bcma.h>
+
+-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
++u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
+ {
+ bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
+ bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
+ return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
+ }
++EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
+
+ void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
+ {
+@@ -54,38 +56,19 @@ void bcma_chipco_regctl_maskset(struct b
}
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
@@ -514,7 +633,7 @@
}
/* Set the resource masks. */
-@@ -93,22 +75,12 @@ static void bcma_pmu_resources_init(stru
+@@ -93,22 +76,12 @@ static void bcma_pmu_resources_init(stru
bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
if (max_msk)
bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
@@ -542,7 +661,7 @@
}
/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
-@@ -122,51 +94,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
+@@ -122,51 +95,69 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
val |= BCMA_CHIPCTL_4331_EXTPA_EN;
if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
@@ -629,7 +748,7 @@
if (cc->pmu.rev == 1)
bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
~BCMA_CC_PMU_CTL_NOILPONW);
-@@ -174,37 +164,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c
+@@ -174,37 +165,31 @@ void bcma_pmu_init(struct bcma_drv_cc *c
bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
BCMA_CC_PMU_CTL_NOILPONW);
@@ -679,7 +798,7 @@
}
return BCMA_CC_PMU_ALP_CLOCK;
}
-@@ -212,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
+@@ -212,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
/* Find the output of the "m" pll divider given pll controls that start with
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
*/
@@ -688,7 +807,7 @@
{
u32 tmp, div, ndiv, p1, p2, fc;
struct bcma_bus *bus = cc->core->bus;
-@@ -221,7 +205,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
+@@ -221,7 +206,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
BUG_ON(!m || m > 4);
@@ -698,7 +817,7 @@
/* Detect failure in clock setting */
tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
if (tmp & 0x40000)
-@@ -240,60 +225,95 @@ static u32 bcma_pmu_clock(struct bcma_dr
+@@ -240,60 +226,95 @@ static u32 bcma_pmu_clock(struct bcma_dr
ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
/* Do calculation in Mhz */
@@ -820,7 +939,7 @@
pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
break;
default:
-@@ -301,10 +321,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
+@@ -301,10 +322,189 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
break;
}
@@ -1054,7 +1173,7 @@
+ { "M25P40", 0x12, 0x10000, 8, },
+
+ { "M25P16", 0x14, 0x10000, 32, },
-+ { "M25P32", 0x14, 0x10000, 64, },
++ { "M25P32", 0x15, 0x10000, 64, },
+ { "M25P64", 0x16, 0x10000, 128, },
+ { "M25FL128", 0x17, 0x10000, 256, },
+ { 0 },
@@ -1199,6 +1318,107 @@
+{
+ mutex_init(&gc->phy_mutex);
+}
+--- /dev/null
++++ b/drivers/bcma/driver_gpio.c
+@@ -0,0 +1,98 @@
++/*
++ * Broadcom specific AMBA
++ * GPIO driver
++ *
++ * Copyright 2011, Broadcom Corporation
++ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include <linux/gpio.h>
++#include <linux/export.h>
++#include <linux/bcma/bcma.h>
++
++#include "bcma_private.h"
++
++static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
++{
++ return container_of(chip, struct bcma_drv_cc, gpio);
++}
++
++static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ return !!bcma_chipco_gpio_in(cc, 1 << gpio);
++}
++
++static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
++}
++
++static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
++ return 0;
++}
++
++static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
++ bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
++ return 0;
++}
++
++static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ bcma_chipco_gpio_control(cc, 1 << gpio, 0);
++ /* clear pulldown */
++ bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
++ /* Set pullup */
++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
++
++ return 0;
++}
++
++static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
++{
++ struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
++
++ /* clear pullup */
++ bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
++}
++
++int bcma_gpio_init(struct bcma_drv_cc *cc)
++{
++ struct gpio_chip *chip = &cc->gpio;
++
++ chip->label = "bcma_gpio";
++ chip->owner = THIS_MODULE;
++ chip->request = bcma_gpio_request;
++ chip->free = bcma_gpio_free;
++ chip->get = bcma_gpio_get_value;
++ chip->set = bcma_gpio_set_value;
++ chip->direction_input = bcma_gpio_direction_input;
++ chip->direction_output = bcma_gpio_direction_output;
++ chip->ngpio = 16;
++ /* There is just one SoC in one device and its GPIO addresses should be
++ * deterministic to address them more easily. The other buses could get
++ * a random base number. */
++ if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
++ chip->base = 0;
++ else
++ chip->base = -1;
++
++ return gpiochip_add(chip);
++}
--- a/drivers/bcma/driver_mips.c
+++ b/drivers/bcma/driver_mips.c
@@ -22,15 +22,15 @@
@@ -1221,36 +1441,112 @@
dev->bus->chipinfo.pkg == 11 &&
dev->id.id == BCMA_CORE_USB20_HOST;
}
-@@ -115,7 +115,7 @@ static void bcma_core_mips_set_irq(struc
+@@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
+ return dev->core_index;
+ flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
+
+- return flag & 0x1F;
++ if (flag)
++ return flag & 0x1F;
++ else
++ return 0x3f;
+ }
+
+ /* Get the MIPS IRQ assignment for a specified device.
+ * If unassigned, 0 is returned.
++ * If disabled, 5 is returned.
++ * If not supported, 6 is returned.
+ */
+ unsigned int bcma_core_mips_irq(struct bcma_device *dev)
+ {
+@@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
+ unsigned int irq;
+
+ irqflag = bcma_core_mips_irqflag(dev);
++ if (irqflag == 0x3f)
++ return 6;
+
+- for (irq = 1; irq <= 4; irq++)
++ for (irq = 0; irq <= 4; irq++)
+ if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
+ (1 << irqflag))
+ return irq;
+
+- return 0;
++ return 5;
+ }
+ EXPORT_SYMBOL(bcma_core_mips_irq);
+
+@@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
~(1 << irqflag));
- else
+- else
- bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
++ else if (oldirq != 5)
+ bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
/* assign the new one */
if (irq == 0) {
-@@ -131,7 +131,7 @@ static void bcma_core_mips_set_irq(struc
+@@ -123,17 +130,17 @@ static void bcma_core_mips_set_irq(struc
+ bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
+ (1 << irqflag));
+ } else {
+- u32 oldirqflag = bcma_read32(mdev,
+- BCMA_MIPS_MIPS74K_INTMASK(irq));
+- if (oldirqflag) {
++ u32 irqinitmask = bcma_read32(mdev,
++ BCMA_MIPS_MIPS74K_INTMASK(irq));
++ if (irqinitmask) {
+ struct bcma_device *core;
+
/* backplane irq line is in use, find out who uses
* it and set user to irq 0
*/
- list_for_each_entry_reverse(core, &bus->cores, list) {
+ list_for_each_entry(core, &bus->cores, list) {
if ((1 << bcma_core_mips_irqflag(core)) ==
- oldirqflag) {
+- oldirqflag) {
++ irqinitmask) {
bcma_core_mips_set_irq(core, 0);
-@@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struc
+ break;
+ }
+@@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
1 << irqflag);
}
- pr_info("set_irq: core 0x%04x, irq %d => %d\n",
- dev->id.id, oldirq + 2, irq + 2);
-+ bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
-+ dev->id.id, oldirq + 2, irq + 2);
++ bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
++ dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
++}
++
++static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
++ u16 coreid, u8 unit)
++{
++ struct bcma_device *core;
++
++ core = bcma_find_core_unit(bus, coreid, unit);
++ if (!core) {
++ bcma_warn(bus,
++ "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
++ coreid, unit);
++ return;
++ }
++
++ bcma_core_mips_set_irq(core, irq);
}
static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
-@@ -161,7 +161,7 @@ static void bcma_core_mips_dump_irq(stru
+ {
+ int i;
+ static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
+- printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
++ printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
+ for (i = 0; i <= 6; i++)
+ printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
+ printk("\n");
+@@ -161,7 +184,7 @@ static void bcma_core_mips_dump_irq(stru
{
struct bcma_device *core;
@@ -1259,7 +1555,7 @@
bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
}
}
-@@ -171,9 +171,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
struct bcma_bus *bus = mcore->core->bus;
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
@@ -1271,7 +1567,7 @@
return 0;
}
EXPORT_SYMBOL(bcma_cpu_clock);
-@@ -181,26 +181,50 @@ EXPORT_SYMBOL(bcma_cpu_clock);
+@@ -181,76 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus = mcore->core->bus;
@@ -1306,7 +1602,7 @@
default:
- pr_err("flash not supported.\n");
+ bcma_err(bus, "Flash type not supported\n");
- }
++ }
+
+ if (cc->core->id.rev == 38 ||
+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
@@ -1314,9 +1610,9 @@
+ bcma_debug(bus, "Found NAND flash\n");
+ bcma_nflash_init(cc);
+ }
-+ }
-+}
-+
+ }
+ }
+
+void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
+{
+ struct bcma_bus *bus = mcore->core->bus;
@@ -1328,10 +1624,11 @@
+ bcma_core_mips_flash_detect(mcore);
+
+ mcore->early_setup_done = true;
- }
-
++}
++
void bcma_core_mips_init(struct bcma_drv_mips *mcore)
-@@ -209,13 +233,17 @@ void bcma_core_mips_init(struct bcma_drv
+ {
+ struct bcma_bus *bus;
struct bcma_device *core;
bus = mcore->core->bus;
@@ -1339,26 +1636,84 @@
+ if (mcore->setup_done)
+ return;
+
-+ bcma_info(bus, "Initializing MIPS core...\n");
-+
-+ bcma_core_mips_early_init(mcore);
++ bcma_debug(bus, "Initializing MIPS core...\n");
- if (!mcore->setup_done)
- mcore->assigned_irqs = 1;
-+ mcore->assigned_irqs = 1;
++ bcma_core_mips_early_init(mcore);
- /* Assign IRQs to all cores on the bus */
+- /* Assign IRQs to all cores on the bus */
- list_for_each_entry_reverse(core, &bus->cores, list) {
-+ list_for_each_entry(core, &bus->cores, list) {
- int mips_irq;
- if (core->irq)
- continue;
-@@ -244,13 +272,8 @@ void bcma_core_mips_init(struct bcma_drv
- break;
+- int mips_irq;
+- if (core->irq)
+- continue;
+-
+- mips_irq = bcma_core_mips_irq(core);
+- if (mips_irq > 4)
+- core->irq = 0;
+- else
+- core->irq = mips_irq + 2;
+- if (core->irq > 5)
+- continue;
+- switch (core->id.id) {
+- case BCMA_CORE_PCI:
+- case BCMA_CORE_PCIE:
+- case BCMA_CORE_ETHERNET:
+- case BCMA_CORE_ETHERNET_GBIT:
+- case BCMA_CORE_MAC_GBIT:
+- case BCMA_CORE_80211:
+- case BCMA_CORE_USB20_HOST:
+- /* These devices get their own IRQ line if available,
+- * the rest goes on IRQ0
+- */
+- if (mcore->assigned_irqs <= 4)
+- bcma_core_mips_set_irq(core,
+- mcore->assigned_irqs++);
+- break;
++ switch (bus->chipinfo.id) {
++ case BCMA_CHIP_ID_BCM4716:
++ case BCMA_CHIP_ID_BCM4748:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
++ break;
++ case BCMA_CHIP_ID_BCM5356:
++ case BCMA_CHIP_ID_BCM47162:
++ case BCMA_CHIP_ID_BCM53572:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
++ break;
++ case BCMA_CHIP_ID_BCM5357:
++ case BCMA_CHIP_ID_BCM4749:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
++ break;
++ case BCMA_CHIP_ID_BCM4706:
++ bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
++ bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
++ 0);
++ bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
++ bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
++ bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
++ 0);
++ break;
++ default:
++ list_for_each_entry(core, &bus->cores, list) {
++ core->irq = bcma_core_mips_irq(core) + 2;
}
++ bcma_err(bus,
++ "Unknown device (0x%x) found, can not configure IRQs\n",
++ bus->chipinfo.id);
}
- pr_info("IRQ reconfiguration done\n");
-+ bcma_info(bus, "IRQ reconfiguration done\n");
++ bcma_debug(bus, "IRQ reconfiguration done\n");
bcma_core_mips_dump_irq(bus);
- if (mcore->setup_done)
@@ -2512,8 +2867,8 @@
}
+EXPORT_SYMBOL_GPL(bcma_find_core);
+
-+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
-+ u8 unit)
++struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
++ u8 unit)
+{
+ struct bcma_device *core;
+
@@ -2546,7 +2901,7 @@
switch (bus->hosttype) {
case BCMA_HOSTTYPE_PCI:
-@@ -111,41 +140,85 @@ static int bcma_register_cores(struct bc
+@@ -111,41 +140,90 @@ static int bcma_register_cores(struct bc
err = device_register(&core->dev);
if (err) {
@@ -2576,6 +2931,11 @@
+ bcma_err(bus, "Error registering NAND flash\n");
+ }
+#endif
++ err = bcma_gpio_init(&bus->drv_cc);
++ if (err == -ENOTSUPP)
++ bcma_debug(bus, "GPIO driver not activated\n");
++ else if (err)
++ bcma_err(bus, "Error registering GPIO driver: %i\n", err);
+
+ if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
+ err = bcma_chipco_watchdog_register(&bus->drv_cc);
@@ -2639,7 +2999,7 @@
if (core) {
bus->drv_cc.core = core;
bcma_core_chipcommon_init(&bus->drv_cc);
-@@ -159,30 +232,47 @@ int bcma_bus_register(struct bcma_bus *b
+@@ -159,30 +237,47 @@ int bcma_bus_register(struct bcma_bus *b
}
/* Init PCIE core */
@@ -2697,7 +3057,7 @@
}
int __init bcma_bus_early_register(struct bcma_bus *bus,
-@@ -196,14 +286,14 @@ int __init bcma_bus_early_register(struc
+@@ -196,14 +291,14 @@ int __init bcma_bus_early_register(struc
bcma_init_bus(bus);
match.manuf = BCMA_MANUF_BCM;
@@ -2714,7 +3074,7 @@
return -1;
}
-@@ -215,25 +305,25 @@ int __init bcma_bus_early_register(struc
+@@ -215,25 +310,25 @@ int __init bcma_bus_early_register(struc
/* Scan for mips core */
err = bcma_bus_scan_early(bus, &match, core_mips);
if (err) {
@@ -2747,7 +3107,7 @@
return 0;
}
-@@ -259,8 +349,7 @@ int bcma_bus_resume(struct bcma_bus *bus
+@@ -259,8 +354,7 @@ int bcma_bus_resume(struct bcma_bus *bus
struct bcma_device *core;
/* Init CC core */
@@ -3760,18 +4120,27 @@
extern bool bcma_core_is_enabled(struct bcma_device *core);
extern void bcma_core_disable(struct bcma_device *core, u32 flags);
extern int bcma_core_enable(struct bcma_device *core, u32 flags);
+@@ -289,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
+ enum bcma_clkmode clkmode);
+ extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
+ bool on);
++extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
+ #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
+ #define BCMA_DMA_TRANSLATION_NONE 0x00000000
+ #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -1,6 +1,8 @@
+@@ -1,6 +1,9 @@
#ifndef LINUX_BCMA_DRIVER_CC_H_
#define LINUX_BCMA_DRIVER_CC_H_
+#include <linux/platform_device.h>
++#include <linux/gpio.h>
+
/** ChipCommon core registers. **/
#define BCMA_CC_ID 0x0000
#define BCMA_CC_ID_ID 0x0000FFFF
-@@ -24,7 +26,7 @@
+@@ -24,7 +27,7 @@
#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
@@ -3780,7 +4149,7 @@
#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
#define BCMA_PLLTYPE_NONE 0x00000000
-@@ -45,6 +47,7 @@
+@@ -45,6 +48,7 @@
#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
@@ -3788,7 +4157,7 @@
#define BCMA_CC_CORECTL 0x0008
#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
-@@ -56,6 +59,9 @@
+@@ -56,6 +60,9 @@
#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
@@ -3798,7 +4167,7 @@
#define BCMA_CC_OTPC 0x0014 /* OTP control */
#define BCMA_CC_OTPC_RECWAIT 0xFF000000
#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
-@@ -72,6 +78,8 @@
+@@ -72,6 +79,8 @@
#define BCMA_CC_OTPP_READ 0x40000000
#define BCMA_CC_OTPP_START 0x80000000
#define BCMA_CC_OTPP_BUSY 0x80000000
@@ -3807,7 +4176,7 @@
#define BCMA_CC_IRQSTAT 0x0020
#define BCMA_CC_IRQMASK 0x0024
#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
-@@ -79,6 +87,22 @@
+@@ -79,6 +88,22 @@
#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
@@ -3830,7 +4199,7 @@
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
#define BCMA_CC_JCMD_START 0x80000000
#define BCMA_CC_JCMD_BUSY 0x80000000
-@@ -108,10 +132,58 @@
+@@ -108,10 +133,58 @@
#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
#define BCMA_CC_FLASHCTL 0x0040
@@ -3889,7 +4258,7 @@
#define BCMA_CC_BCAST_ADDR 0x0050
#define BCMA_CC_BCAST_DATA 0x0054
#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
-@@ -181,6 +253,45 @@
+@@ -181,6 +254,45 @@
#define BCMA_CC_FLASH_CFG 0x0128
#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
#define BCMA_CC_FLASH_WAITCNT 0x012C
@@ -3935,7 +4304,7 @@
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
#define BCMA_CC_UART0_DATA 0x0300
-@@ -240,7 +351,60 @@
+@@ -240,7 +352,60 @@
#define BCMA_CC_PLLCTL_ADDR 0x0660
#define BCMA_CC_PLLCTL_DATA 0x0664
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
@@ -3997,7 +4366,7 @@
/* Divider allocation in 4716/47162/5356 */
#define BCMA_CC_PMU5_MAINPLL_CPU 1
-@@ -256,6 +420,15 @@
+@@ -256,6 +421,15 @@
/* 4706 PMU */
#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
@@ -4013,7 +4382,7 @@
/* ALP clock on pre-PMU chips */
#define BCMA_CC_PMU_ALP_CLOCK 20000000
-@@ -284,6 +457,19 @@
+@@ -284,6 +458,19 @@
#define BCMA_CC_PPL_PCHI_OFF 5
#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
@@ -4033,7 +4402,7 @@
/* BCM4331 ChipControl numbers. */
#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
-@@ -297,9 +483,25 @@
+@@ -297,9 +484,25 @@
#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
@@ -4059,7 +4428,7 @@
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
-@@ -310,11 +512,35 @@ struct bcma_chipcommon_pmu {
+@@ -310,11 +513,35 @@ struct bcma_chipcommon_pmu {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
@@ -4095,7 +4464,7 @@
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -330,15 +556,24 @@ struct bcma_drv_cc {
+@@ -330,15 +557,30 @@ struct bcma_drv_cc {
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
@@ -4117,10 +4486,16 @@
#endif /* CONFIG_BCMA_DRIVER_MIPS */
+ u32 ticks_per_ms;
+ struct platform_device *watchdog;
++
++ /* Lock for GPIO register access. */
++ spinlock_t gpio_lock;
++#ifdef CONFIG_BCMA_DRIVER_GPIO
++ struct gpio_chip gpio;
++#endif
};
/* Register access */
-@@ -355,14 +590,14 @@ struct bcma_drv_cc {
+@@ -355,14 +597,14 @@ struct bcma_drv_cc {
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
@@ -4137,7 +4512,12 @@
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-@@ -378,6 +613,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
+@@ -375,9 +617,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
+ u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
+ u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
+ u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
++u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
++u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
/* PMU support */
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
@@ -4145,7 +4525,7 @@
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
u32 value);
-@@ -387,5 +623,6 @@ extern void bcma_chipco_chipctl_maskset(
+@@ -387,5 +632,6 @@ extern void bcma_chipco_chipctl_maskset(
u32 offset, u32 mask, u32 set);
extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set);
@@ -4257,12 +4637,12 @@
+#endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
--- a/include/linux/bcma/bcma_driver_mips.h
+++ b/include/linux/bcma/bcma_driver_mips.h
-@@ -35,13 +35,16 @@ struct bcma_device;
+@@ -35,13 +35,15 @@ struct bcma_device;
struct bcma_drv_mips {
struct bcma_device *core;
u8 setup_done:1;
+- unsigned int assigned_irqs;
+ u8 early_setup_done:1;
- unsigned int assigned_irqs;
};
#ifdef CONFIG_BCMA_DRIVER_MIPS