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| author | Felix Fietkau <nbd@openwrt.org> | 2015-01-24 19:42:06 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-01-24 19:42:06 +0000 |
| commit | 4bfb00d02d6537fee9557d989601bc235fa81116 (patch) | |
| tree | a0afadd52a96538fee50829f7c06d84fce4b2cb2 /target/linux/generic/files/drivers/net/phy/ar8327.h | |
| parent | 95e0b242c20cd8fe135e989cdad76405d38cca25 (diff) | |
| download | upstream-4bfb00d02d6537fee9557d989601bc235fa81116.tar.gz upstream-4bfb00d02d6537fee9557d989601bc235fa81116.tar.bz2 upstream-4bfb00d02d6537fee9557d989601bc235fa81116.zip | |
ar8216: add swconfig attribute to display ARL table on AR8327/AR8337
Add global read-only swconfig attribute "arl_table" to display the
address resolution table.
So far the chip-specific part is implemented for AR8327/AR8337 only
as I don't have the datasheets for the other AR8XXX chips.
Successfully tested on TL-WDR4300 (AR8327rev2)
and TL-WDR4900 (AR8327rev4).
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44104 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/ar8327.h')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8327.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.h b/target/linux/generic/files/drivers/net/phy/ar8327.h index f0ef013cb6..29eeb6271d 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8327.h +++ b/target/linux/generic/files/drivers/net/phy/ar8327.h @@ -114,8 +114,29 @@ #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 #define AR8327_REG_ATU_DATA0 0x600 +#define AR8327_ATU_ADDR0 BITS(0, 8) +#define AR8327_ATU_ADDR0_S 0 +#define AR8327_ATU_ADDR1 BITS(8, 8) +#define AR8327_ATU_ADDR1_S 8 +#define AR8327_ATU_ADDR2 BITS(16, 8) +#define AR8327_ATU_ADDR2_S 16 +#define AR8327_ATU_ADDR3 BITS(24, 8) +#define AR8327_ATU_ADDR3_S 24 #define AR8327_REG_ATU_DATA1 0x604 +#define AR8327_ATU_ADDR4 BITS(0, 8) +#define AR8327_ATU_ADDR4_S 0 +#define AR8327_ATU_ADDR5 BITS(8, 8) +#define AR8327_ATU_ADDR5_S 8 +#define AR8327_ATU_PORTS BITS(16, 7) +#define AR8327_ATU_PORT0 BIT(16) +#define AR8327_ATU_PORT1 BIT(17) +#define AR8327_ATU_PORT2 BIT(18) +#define AR8327_ATU_PORT3 BIT(19) +#define AR8327_ATU_PORT4 BIT(20) +#define AR8327_ATU_PORT5 BIT(21) +#define AR8327_ATU_PORT6 BIT(22) #define AR8327_REG_ATU_DATA2 0x608 +#define AR8327_ATU_STATUS BITS(0, 4) #define AR8327_REG_ATU_FUNC 0x60c #define AR8327_ATU_FUNC_OP BITS(0, 4) |