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| author | Jeff Kletsky <git-commits@allycomm.com> | 2019-10-24 09:54:11 -0700 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2019-10-24 23:07:47 +0200 |
| commit | b9d58f7e066fdd58be173c56e0f3ff3664d08059 (patch) | |
| tree | 7f85a59e1869a9a4ef5501357c67f8a97b56dc76 /target/linux/generic/backport-4.19/460-v5.3-mtd-spinand-Define-macros-for-page-read-ops-with-thr.patch | |
| parent | 29b4f084053bdbd210f16f8ad85b793784c81438 (diff) | |
| download | upstream-b9d58f7e066fdd58be173c56e0f3ff3664d08059.tar.gz upstream-b9d58f7e066fdd58be173c56e0f3ff3664d08059.tar.bz2 upstream-b9d58f7e066fdd58be173c56e0f3ff3664d08059.zip | |
kernel: mtd: spinand: Backport chip definitions
generic: Add/rename patches for upstream consistency
ipq40xx: generic-level patch replaces same-source patches-4.19/
082-v4.20-mtd-spinand-winbond-Add-support-for-W25N01GV.patch
The SPI-NAND framework from Linux uses common driver code that is then
"tuned" by a tiny struct of chip-specific data that describes
available commands, timing, and layout (data and OOB data). Several
manufacturers and chips have been added since 4.19, several of which
are used in devices already supported by OpenWrt (typically with no or
"legacy" access to their NAND memory). This commit catches up the
supported-chip definitions through Linux 5.2-rc6 and linux/next.
The driver is only compiled for platforms with CONFIG_MTD_SPI_NAND=y.
This presently includes ipq40xx and pistachio, with the addition of
ath79-nand in these commits (and not ath79-generic or ath79-tiny).
Upstream patches refreshed against 4.19.75
Build-tested-on: ipq40xx
Run-tested-on: ath79-nand
Signed-off-by: Jeff Kletsky <git-commits@allycomm.com>
Diffstat (limited to 'target/linux/generic/backport-4.19/460-v5.3-mtd-spinand-Define-macros-for-page-read-ops-with-thr.patch')
| -rw-r--r-- | target/linux/generic/backport-4.19/460-v5.3-mtd-spinand-Define-macros-for-page-read-ops-with-thr.patch | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/target/linux/generic/backport-4.19/460-v5.3-mtd-spinand-Define-macros-for-page-read-ops-with-thr.patch b/target/linux/generic/backport-4.19/460-v5.3-mtd-spinand-Define-macros-for-page-read-ops-with-thr.patch new file mode 100644 index 0000000000..c28ae1d797 --- /dev/null +++ b/target/linux/generic/backport-4.19/460-v5.3-mtd-spinand-Define-macros-for-page-read-ops-with-thr.patch @@ -0,0 +1,81 @@ +From d014717d50b1efd011a3a028ce92563a4dc9bae5 Mon Sep 17 00:00:00 2001 +From: Jeff Kletsky <git-commits@allycomm.com> +Date: Wed, 22 May 2019 15:05:53 -0700 +Subject: [PATCH 1/3] mtd: spinand: Define macros for page-read ops with + three-byte addresses + +The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses +for its page-read ops. + +http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/ + +Signed-off-by: Jeff Kletsky <git-commits@allycomm.com> +Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> +Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> +--- + include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -68,30 +68,60 @@ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 1)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 1), \ ++ SPI_MEM_OP_DUMMY(ndummy, 1), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 1)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ + SPI_MEM_OP_ADDR(2, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 2)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 1), \ ++ SPI_MEM_OP_DUMMY(ndummy, 1), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 2)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ + SPI_MEM_OP_ADDR(2, addr, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 4)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 1), \ ++ SPI_MEM_OP_DUMMY(ndummy, 1), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 4)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ + SPI_MEM_OP_ADDR(2, addr, 2), \ + SPI_MEM_OP_DUMMY(ndummy, 2), \ + SPI_MEM_OP_DATA_IN(len, buf, 2)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 2), \ ++ SPI_MEM_OP_DUMMY(ndummy, 2), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 2)) ++ + #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ + SPI_MEM_OP_ADDR(2, addr, 4), \ + SPI_MEM_OP_DUMMY(ndummy, 4), \ + SPI_MEM_OP_DATA_IN(len, buf, 4)) + ++#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \ ++ SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ ++ SPI_MEM_OP_ADDR(3, addr, 4), \ ++ SPI_MEM_OP_DUMMY(ndummy, 4), \ ++ SPI_MEM_OP_DATA_IN(len, buf, 4)) ++ + #define SPINAND_PROG_EXEC_OP(addr) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ + SPI_MEM_OP_ADDR(3, addr, 1), \ |