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authorJonas Gorski <jogo@openwrt.org>2015-12-02 22:24:46 +0000
committerJonas Gorski <jogo@openwrt.org>2015-12-02 22:24:46 +0000
commite395433178224ff1e2a6053105d12936b46c7576 (patch)
tree6fd6e2bb8019d78d1b8a57d63516ebbe3cff47f6 /target/linux/brcm63xx/patches-4.4/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch
parent621677154f39f2e0b698a558b8b795db84a8e014 (diff)
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brcm63xx: add linux 4.4 support
Only netboot tested. Flash at your own risk. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 47702
Diffstat (limited to 'target/linux/brcm63xx/patches-4.4/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch')
-rw-r--r--target/linux/brcm63xx/patches-4.4/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch71
1 files changed, 71 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-4.4/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch b/target/linux/brcm63xx/patches-4.4/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch
new file mode 100644
index 0000000000..10edbc4dda
--- /dev/null
+++ b/target/linux/brcm63xx/patches-4.4/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch
@@ -0,0 +1,71 @@
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -586,6 +586,9 @@
+ #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
+ #define TIMER_CTL_ENABLE_MASK (1 << 31)
+
++/* Clock reset control (63268 only) */
++#define TIMER_CLK_RST_CTL_REG 0x2c
++#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18)
+
+ /*************************************************************************
+ * _REG relative to RSET_WDT
+@@ -1533,6 +1536,11 @@
+ #define STRAPBUS_63268_FCVO_SHIFT 21
+ #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
+
++#define MISC_IDDQ_CTRL_6328_REG 0x48
++#define MISC_IDDQ_CTRL_63268_REG 0x4c
++
++#define IDDQ_CTRL_63268_USBH (1 << 4)
++
+ #define MISC_STRAPBUS_6328_REG 0x240
+ #define STRAPBUS_6328_FCVO_SHIFT 7
+ #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -62,6 +62,26 @@ static void bcm_ub_hwclock_set(u32 mask,
+ bcm_perf_writel(reg, PERF_UB_CKCTL_REG);
+ }
+
++static void bcm_misc_iddq_set(u32 mask, int enable)
++{
++ u32 offset;
++ u32 reg;
++
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
++ offset = MISC_IDDQ_CTRL_6328_REG;
++ else if (BCMCPU_IS_63268())
++ offset = MISC_IDDQ_CTRL_63268_REG;
++ else
++ return;
++
++ reg = bcm_misc_readl(offset);
++ if (enable)
++ reg &= ~mask;
++ else
++ reg |= mask;
++ bcm_misc_writel(reg, offset);
++}
++
+ /*
+ * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
+ */
+@@ -199,7 +219,17 @@ static void usbh_set(struct clk *clk, in
+ } else if (BCMCPU_IS_6368()) {
+ bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
+ } else if (BCMCPU_IS_63268()) {
++ u32 reg;
++
+ bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
++ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
++ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
++ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG);
++ if (enable)
++ reg |= CLK_RST_CTL_USB_REF_CLK_EN;
++ else
++ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN;
++ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG);
+ } else {
+ return;
+ }