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authorJonas Gorski <jogo@openwrt.org>2012-03-28 20:42:25 +0000
committerJonas Gorski <jogo@openwrt.org>2012-03-28 20:42:25 +0000
commit78fb818f7c46f45272c1ef00c40febe6fc30ace5 (patch)
tree2e12755cb3c115cfdafb9fa9c68810d76032a704 /target/linux/brcm63xx/patches-3.3/003-MIPS-BCM63XX-add-IRQ_SPI-and-CPU-specific-SPI-IRQ-va.patch
parenta2adca6ee9a731aa2b0ee7ca246db8f941266ed6 (diff)
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bcm63xx: replace SPI driver with latest upstream version
SVN-Revision: 31130
Diffstat (limited to 'target/linux/brcm63xx/patches-3.3/003-MIPS-BCM63XX-add-IRQ_SPI-and-CPU-specific-SPI-IRQ-va.patch')
-rw-r--r--target/linux/brcm63xx/patches-3.3/003-MIPS-BCM63XX-add-IRQ_SPI-and-CPU-specific-SPI-IRQ-va.patch68
1 files changed, 68 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.3/003-MIPS-BCM63XX-add-IRQ_SPI-and-CPU-specific-SPI-IRQ-va.patch b/target/linux/brcm63xx/patches-3.3/003-MIPS-BCM63XX-add-IRQ_SPI-and-CPU-specific-SPI-IRQ-va.patch
new file mode 100644
index 0000000000..b4c787c52a
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/003-MIPS-BCM63XX-add-IRQ_SPI-and-CPU-specific-SPI-IRQ-va.patch
@@ -0,0 +1,68 @@
+From 04456614952a9a848192253439b4e361f0321cb5 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 25 Jan 2012 17:39:51 +0100
+Subject: [PATCH 05/63] MIPS: BCM63XX: add IRQ_SPI and CPU specific SPI IRQ values
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -478,6 +478,7 @@ static inline unsigned long bcm63xx_regs
+ */
+ enum bcm63xx_irq {
+ IRQ_TIMER = 0,
++ IRQ_SPI,
+ IRQ_UART0,
+ IRQ_UART1,
+ IRQ_DSL,
+@@ -509,6 +510,7 @@ enum bcm63xx_irq {
+ * 6338 irqs
+ */
+ #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
++#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
+ #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+ #define BCM_6338_UART1_IRQ 0
+ #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
+@@ -539,6 +541,7 @@ enum bcm63xx_irq {
+ * 6345 irqs
+ */
+ #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
++#define BCM_6345_SPI_IRQ 0
+ #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+ #define BCM_6345_UART1_IRQ 0
+ #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
+@@ -569,6 +572,7 @@ enum bcm63xx_irq {
+ * 6348 irqs
+ */
+ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
++#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
+ #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+ #define BCM_6348_UART1_IRQ 0
+ #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
+@@ -599,6 +603,7 @@ enum bcm63xx_irq {
+ * 6358 irqs
+ */
+ #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
++#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
+ #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+ #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
+ #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
+@@ -638,6 +643,7 @@ enum bcm63xx_irq {
+ #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
+
+ #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
++#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
+ #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
+ #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
+ #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
+@@ -677,6 +683,7 @@ extern const int *bcm63xx_irqs;
+
+ #define __GEN_CPU_IRQ_TABLE(__cpu) \
+ [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
++ [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
+ [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
+ [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
+ [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \