brcm2708: rename all patches from raspberrypi git tree to use 950 prefix

Right now all brcm2708 patches are extracted from the non-mainline
raspberrypi/linux git tree. Many of them are hacks and/or are unneeded
in LEDE. Raspberry Pi is getting better and better mainline support so
it would be nice to finally start maintaining patches in a cleaner way:
1) Backport patches accepted in upstream tree
2) Start using upstream drivers
3) Pick only these patches that are needed for more complete support

Handling above tasks requires grouping patches - ideally using the same
prefixes as generic ones. It means we should rename existing patches to
use some high prefix. This will allow e.g. use 0xx for backported code.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Stijn Tintel <stijn@linux-ipv6.be>

1 files changed, 27 insertions, 0 deletions

diff --git a/target/linux/brcm2708/patches-4.9/950-0194-clk-bcm2835-Correct-the-prediv-logic.patch b/target/linux/brcm2708/patches-4.9/950-0194-clk-bcm2835-Correct-the-prediv-logic.patch
new file mode 100644
index 0000000000..c81194fe69
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.9/950-0194-clk-bcm2835-Correct-the-prediv-logic.patch
@@ -0,0 +1,27 @@
+From a9913dccdeaabca37343d0d8b0a48cda1e434e02 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Wed, 1 Mar 2017 16:06:53 +0000
+Subject: [PATCH] clk-bcm2835: Correct the prediv logic
+
+If a clock has the prediv flag set, both the integer and fractional
+parts must be scaled when calculating the resulting frequency.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ drivers/clk/bcm/clk-bcm2835.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -616,8 +616,10 @@ static unsigned long bcm2835_pll_get_rat
+ 	using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
+ 		data->ana->fb_prediv_mask;
+ 
+-	if (using_prediv)
++	if (using_prediv) {
+ 		ndiv *= 2;
++		fdiv *= 2;
++	}
+ 
+ 	return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
+ }