bmips: add new target

This target has full device tree support, thus reducing the number of
patches needed for bcm63xx, in which there's a patch for every board.

The intention is to start with a minimal amount of downstream patches and
start upstreaming all of them.

Current status:
 - Enabling EHCI/OHCI on BCM6358 causes a kernel panic.
 - BCM63268 lacks Timer Clocks/Reset support.
 - No PCI/PCIe drivers.
 - No ethernet drivers.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>

1 files changed, 68 insertions, 0 deletions

diff --git a/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h b/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h
new file mode 100644
index 0000000000..1f5192d9fe
--- /dev/null
+++ b/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H
+
+#define BCM6328_IRQ_NAND		0
+#define BCM6328_IRQ_PCM			1
+#define BCM6328_IRQ_PCM_DMA0		2
+#define BCM6328_IRQ_PCM_DMA1		3
+#define BCM6328_IRQ_USBS		4
+#define BCM6328_IRQ_USB_CTL_RX_DMA	5
+#define BCM6328_IRQ_USB_CTL_TX_DMA	6
+#define BCM6328_IRQ_USB_BULK_RX_DMA	7
+#define BCM6328_IRQ_USB_BULK_TX_DMA	8
+#define BCM6328_IRQ_USB_ISO_RX_DMA	9
+#define BCM6328_IRQ_USB_ISO_TX_DMA	10
+#define BCM6328_IRQ_DG			11
+#define BCM6328_IRQ_EPHY		12
+#define BCM6328_IRQ_EPHY_EN0N		13
+#define BCM6328_IRQ_EPHY_EN1N		14
+#define BCM6328_IRQ_EPHY_EN2N		15
+#define BCM6328_IRQ_EPHY_EN3N		16
+#define BCM6328_IRQ_EPHY_EN0		17
+#define BCM6328_IRQ_EPHY_EN1		18
+#define BCM6328_IRQ_EPHY_EN2		19
+#define BCM6328_IRQ_EPHY_EN3		20
+#define BCM6328_IRQ_XDSL		21
+#define BCM6328_IRQ_PCIE_EP		22
+#define BCM6328_IRQ_PCIE_RC		23
+#define BCM6328_IRQ_EXTO		24
+#define BCM6328_IRQ_EXT1		25
+#define BCM6328_IRQ_EXT2		26
+#define BCM6328_IRQ_EXT3		27
+#define BCM6328_IRQ_UART0		28
+#define BCM6328_IRQ_HSSPI		29
+#define BCM6328_IRQ_WAKE_ON_IRQ		30
+#define BCM6328_IRQ_TIMER		31
+#define BCM6328_IRQ_ENETSW_RX_DMA0	32
+#define BCM6328_IRQ_ENETSW_RX_DMA1	33
+#define BCM6328_IRQ_ENETSW_TX_DMA0	34
+#define BCM6328_IRQ_ENETSW_TX_DMA1	35
+#define BCM6328_IRQ_UART1		39
+#define BCM6328_IRQ_ENETSW		40
+#define BCM6328_IRQ_OHCI		41
+#define BCM6328_IRQ_EHCI		42
+#define BCM6328_IRQ_ATM_DMA0		43
+#define BCM6328_IRQ_ATM_DMA1		44
+#define BCM6328_IRQ_ATM_DMA2		45
+#define BCM6328_IRQ_ATM_DMA3		46
+#define BCM6328_IRQ_ATM_DMA4		47
+#define BCM6328_IRQ_ATM_DMA5		48
+#define BCM6328_IRQ_ATM_DMA6		49
+#define BCM6328_IRQ_ATM_DMA7		50
+#define BCM6328_IRQ_ATM_DMA8		51
+#define BCM6328_IRQ_ATM_DMA9		52
+#define BCM6328_IRQ_ATM_DMA10		53
+#define BCM6328_IRQ_ATM_DMA11		54
+#define BCM6328_IRQ_ATM_DMA12		55
+#define BCM6328_IRQ_ATM_DMA13		56
+#define BCM6328_IRQ_ATM_DMA14		57
+#define BCM6328_IRQ_ATM_DMA15		58
+#define BCM6328_IRQ_ATM_DMA16		59
+#define BCM6328_IRQ_ATM_DMA17		60
+#define BCM6328_IRQ_ATM_DMA18		61
+#define BCM6328_IRQ_ATM_DMA19		62
+#define BCM6328_IRQ_SAR			63
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H */