bmips: add new target

This target has full device tree support, thus reducing the number of
patches needed for bcm63xx, in which there's a patch for every board.

The intention is to start with a minimal amount of downstream patches and
start upstreaming all of them.

Current status:
 - Enabling EHCI/OHCI on BCM6358 causes a kernel panic.
 - BCM63268 lacks Timer Clocks/Reset support.
 - No PCI/PCIe drivers.
 - No ethernet drivers.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>

1 files changed, 86 insertions, 0 deletions

diff --git a/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h b/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h
new file mode 100644
index 0000000000..84a5f44611
--- /dev/null
+++ b/target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H
+
+#define BCM63268_IRQ_TIMER		0
+#define BCM63268_IRQ_ENETSW_RX_DMA0	1
+#define BCM63268_IRQ_ENETSW_RX_DMA1	2
+#define BCM63268_IRQ_ENETSW_RX_DMA2	3
+#define BCM63268_IRQ_ENETSW_RX_DMA3	4
+#define BCM63268_IRQ_UART0		5
+#define BCM63268_IRQ_HSSPI		6
+#define BCM63268_IRQ_WLAN		7
+#define BCM63268_IRQ_IPSEC		8
+#define BCM63268_IRQ_OHCI		9
+#define BCM63268_IRQ_EHCI		10
+#define BCM63268_IRQ_USBS		11
+#define BCM63268_IRQ_PCM		12
+#define BCM63268_IRQ_EPHY		13
+#define BCM63268_IRQ_DG			14
+#define BCM63268_IRQ_EPHY0_EN		15
+#define BCM63268_IRQ_EPHY1_EN		16
+#define BCM63268_IRQ_EPHY2_EN		17
+#define BCM63268_IRQ_GPHY_EN		18
+#define BCM63268_IRQ_USB_CTL_RX_DMA	19
+#define BCM63268_IRQ_USB_BULK_RX_DMA	20
+#define BCM63268_IRQ_ISO_RX_DMA		21
+#define BCM63268_IRQ_IPSEC_DMA0		22
+#define BCM63268_IRQ_XDSL		23
+#define BCM63268_IRQ_FAP0		24
+#define BCM63268_IRQ_FAP1		25
+#define BCM63268_IRQ_ATM_DMA0		26
+#define BCM63268_IRQ_ATM_DMA1		27
+#define BCM63268_IRQ_ATM_DMA2		28
+#define BCM63268_IRQ_ATM_DMA3		29
+#define BCM63268_IRQ_WAKE_ON_IRQ	30
+#define BCM63268_IRQ_GPHY		31
+#define BCM63268_IRQ_DECT0              32		
+#define BCM63268_IRQ_DECT1		33
+#define BCM63268_IRQ_UART1              34		
+#define BCM63268_IRQ_WLAN_GPIO		35
+#define BCM63268_IRQ_USB_CTL_TX_DMA	36
+#define BCM63268_IRQ_USB_BULK_TX_DMA	37
+#define BCM63268_IRQ_ISO_TX_DMA		38
+#define BCM63268_IRQ_IPSEC_DMA1		39
+#define BCM63268_IRQ_PCIE_RC		40
+#define BCM63268_IRQ_PCIE_EP		41
+#define BCM63268_IRQ_PCM_DMA0		42
+#define BCM63268_IRQ_PCM_DMA1		43
+#define BCM63268_IRQ_EXT0		44
+#define BCM63268_IRQ_EXT1		45
+#define BCM63268_IRQ_EXT2		46
+#define BCM63268_IRQ_EXT3		47
+#define BCM63268_IRQ_ENETSW		48
+#define BCM63268_IRQ_SAR		49
+#define BCM63268_IRQ_NAND		50
+#define BCM63268_IRQ_RING_OSC		52
+#define BCM63268_IRQ_USB_CONNECT	53
+#define BCM63268_IRQ_USB_DISCONNECT	54
+#define BCM63268_IRQ_PER_MBOX0		55
+#define BCM63268_IRQ_PER_MBOX1		56
+#define BCM63268_IRQ_PER_MBOX2		57
+#define BCM63268_IRQ_PER_MBOX3		58
+#define BCM63268_IRQ_ATM_DMA4		59
+#define BCM63268_IRQ_ATM_DMA5		60
+#define BCM63268_IRQ_ATM_DMA6		61
+#define BCM63268_IRQ_ATM_DMA7		62
+#define BCM63268_IRQ_ENETSW_TX_DMA0	64
+#define BCM63268_IRQ_ENETSW_TX_DMA1	65
+#define BCM63268_IRQ_ENETSW_TX_DMA2	66
+#define BCM63268_IRQ_ENETSW_TX_DMA3	67
+#define BCM63268_IRQ_ATM_DMA8		68
+#define BCM63268_IRQ_ATM_DMA9		69
+#define BCM63268_IRQ_ATM_DMA10		70
+#define BCM63268_IRQ_ATM_DMA11		71
+#define BCM63268_IRQ_ATM_DMA12		72
+#define BCM63268_IRQ_ATM_DMA13		73
+#define BCM63268_IRQ_ATM_DMA14		74
+#define BCM63268_IRQ_ATM_DMA15		75
+#define BCM63268_IRQ_ATM_DMA16		76
+#define BCM63268_IRQ_ATM_DMA17		77
+#define BCM63268_IRQ_ATM_DMA18		78
+#define BCM63268_IRQ_ATM_DMA19		79
+#define BCM63268_IRQ_LSSPI		80
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H */