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| author | Daniel Golle <daniel@makrotopia.org> | 2022-03-21 01:16:48 +0000 |
|---|---|---|
| committer | Paul Spooren <mail@aparcar.org> | 2022-03-21 11:36:30 +0000 |
| commit | 3a14580411adfb75f9a44eded9f41245b9e44606 (patch) | |
| tree | c3002cc1a0948bfedc4475d7276da0b3ebd4775c /target/linux/bcm63xx/patches-5.4/331-MIPS-BCM63XX-define-variant-id-field.patch | |
| parent | 9f9477b2751231d57cdd8c227149b88c93491d93 (diff) | |
| download | upstream-3a14580411adfb75f9a44eded9f41245b9e44606.tar.gz upstream-3a14580411adfb75f9a44eded9f41245b9e44606.tar.bz2 upstream-3a14580411adfb75f9a44eded9f41245b9e44606.zip | |
kernel: delete Linux 5.4 config and patches
As the upcoming release will be based on Linux 5.10 only, remove all
kernel configuration as well as patches for Linux 5.4.
There were no targets still actively using Linux 5.4.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/bcm63xx/patches-5.4/331-MIPS-BCM63XX-define-variant-id-field.patch')
| -rw-r--r-- | target/linux/bcm63xx/patches-5.4/331-MIPS-BCM63XX-define-variant-id-field.patch | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/target/linux/bcm63xx/patches-5.4/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/bcm63xx/patches-5.4/331-MIPS-BCM63XX-define-variant-id-field.patch deleted file mode 100644 index 57af836858..0000000000 --- a/target/linux/bcm63xx/patches-5.4/331-MIPS-BCM63XX-define-variant-id-field.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Sat, 7 Dec 2013 14:22:41 +0100 -Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field - -Some SoC have a variant id field in the chip id register. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -10,6 +10,8 @@ - #define PERF_REV_REG 0x0 - #define REV_CHIPID_SHIFT 16 - #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) -+#define REV_VARID_SHIFT 12 -+#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) - #define REV_REVID_SHIFT 0 - #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) - |