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authorNick Hainke <vincent@systemli.org>2021-12-27 02:17:43 +0100
committerChristian Lamparter <chunkeey@gmail.com>2021-12-29 22:55:16 +0100
commit83b5fbddf28e943e8c90b4099a1e36d158f5995c (patch)
treeebfdbe3be27d8238e7a48f669f41b84d46b8bf5a /target/linux/ath79
parent6bfc8bb4a37903bd1d3bb7e7824d89f3a2cca6a1 (diff)
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kernel: 5.10: add patches to fix macronix flash
mtd: spi-nor: locking support for MX25L6405D Macronix MX25L6405D supports locking with four block-protection bits. Currently, the driver only sets three bits. If the bootloader does not sustain the flash chip in an unlocked state, the flash might be non-writeable. Add the corresponding flag to enable locking support with four bits in the status register. mtd: spi-nor: disable 16-bit-sr for macronix Macronix flash chips seem to consist of only one status register. These chips will not work with the "16-bit Write Status (01h) Command". Disable SNOR_F_HAS_16BIT_SR for all Macronix chips. Refreshed: - 0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch Fixes: 15aa53d7ee65 ("ath79: switch to Kernel 5.10") Signed-off-by: Nick Hainke <vincent@systemli.org>
Diffstat (limited to 'target/linux/ath79')
-rw-r--r--target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch b/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch
index 317bef2201..e99d067c48 100644
--- a/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch
+++ b/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch
@@ -21,7 +21,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
-@@ -50,7 +50,8 @@ static const struct flash_info macronix_
+@@ -51,7 +51,8 @@ static const struct flash_info macronix_
{ "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
{ "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },