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| author | Shiji Yang <yangshiji66@qq.com> | 2022-10-27 13:17:12 +0800 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2022-11-09 22:55:33 +0100 |
| commit | 8d4c22a9561dc43e81cfa15fcfdec86c052792cd (patch) | |
| tree | 9df651b3e81371485cce32f13780ec57c61aa34b /target/linux/ath79/dts/qca955x.dtsi | |
| parent | 520c90854ca73eb6c3d8feeda59766c90bdd4144 (diff) | |
| download | upstream-8d4c22a9561dc43e81cfa15fcfdec86c052792cd.tar.gz upstream-8d4c22a9561dc43e81cfa15fcfdec86c052792cd.tar.bz2 upstream-8d4c22a9561dc43e81cfa15fcfdec86c052792cd.zip | |
ath79: add missing clock name strings in SoC dtsi
For all SoC in the ath79 target, the PLL controller provides 3 main
clocks "cpu", "ddr" and "ahb" through the input clock "ref".
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Diffstat (limited to 'target/linux/ath79/dts/qca955x.dtsi')
| -rw-r--r-- | target/linux/ath79/dts/qca955x.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/ath79/dts/qca955x.dtsi b/target/linux/ath79/dts/qca955x.dtsi index b6e08f9f12..0541c4e373 100644 --- a/target/linux/ath79/dts/qca955x.dtsi +++ b/target/linux/ath79/dts/qca955x.dtsi @@ -119,6 +119,7 @@ clock-output-names = "cpu", "ddr", "ahb"; clocks = <&extosc>; + clock-names = "ref"; }; wdt: wdt@18060008 { |