From 8d4c22a9561dc43e81cfa15fcfdec86c052792cd Mon Sep 17 00:00:00 2001 From: Shiji Yang Date: Thu, 27 Oct 2022 13:17:12 +0800 Subject: ath79: add missing clock name strings in SoC dtsi For all SoC in the ath79 target, the PLL controller provides 3 main clocks "cpu", "ddr" and "ahb" through the input clock "ref". Signed-off-by: Shiji Yang --- target/linux/ath79/dts/qca955x.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'target/linux/ath79/dts/qca955x.dtsi') diff --git a/target/linux/ath79/dts/qca955x.dtsi b/target/linux/ath79/dts/qca955x.dtsi index b6e08f9f12..0541c4e373 100644 --- a/target/linux/ath79/dts/qca955x.dtsi +++ b/target/linux/ath79/dts/qca955x.dtsi @@ -119,6 +119,7 @@ clock-output-names = "cpu", "ddr", "ahb"; clocks = <&extosc>; + clock-names = "ref"; }; wdt: wdt@18060008 { -- cgit v1.2.3