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authorDavid Bauer <mail@david-bauer.net>2018-08-06 16:21:02 +0200
committerJohn Crispin <john@phrozen.org>2018-08-08 08:38:45 +0200
commit4b9680f138264e73517a51f7155d96bf4a96b682 (patch)
treec07a7cf87320f1325e06ae77fc624b76c0935649 /target/linux/ath79/dts/qca9557.dtsi
parent5107ba23744989fd9ed68f40ed7e0ded5966e3b7 (diff)
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ath79: fix QCA9557 eth PLL settings
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both eth0 and eth1, therefore PLL settings won't be applied. This commit fixes this behavior. Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ath79/dts/qca9557.dtsi')
-rw-r--r--target/linux/ath79/dts/qca9557.dtsi8
1 files changed, 7 insertions, 1 deletions
diff --git a/target/linux/ath79/dts/qca9557.dtsi b/target/linux/ath79/dts/qca9557.dtsi
index c3874bc41e..992ccff1e7 100644
--- a/target/linux/ath79/dts/qca9557.dtsi
+++ b/target/linux/ath79/dts/qca9557.dtsi
@@ -109,7 +109,7 @@
pll: pll-controller@18050000 {
compatible = "qca,ar9557-pll",
- "qca,qca9550-pll";
+ "qca,qca9550-pll", "syscon";
reg = <0x18050000 0x50>;
#clock-cells = <1>;
@@ -295,6 +295,9 @@
&eth0 {
compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
+ pll-reg = <0 0x28 0>;
+ pll-handle = <&pll>;
+
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-mode = "rgmii";
@@ -310,6 +313,9 @@
&eth1 {
compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
+ pll-reg = <0 0x48 0>;
+ pll-handle = <&pll>;
+
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-mode = "sgmii";