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| author | Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> | 2018-05-31 19:49:08 +0000 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-06-01 08:25:14 +0200 |
| commit | 7dca1bae82bfd2ce3486cebf856b9f25a43e61c4 (patch) | |
| tree | d8cce8702008672e6d4850ea9a8b5c0664109bfc /target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch | |
| parent | 5b0c899bfd65def36776d34a8fa8a22d3163fba2 (diff) | |
| download | upstream-7dca1bae82bfd2ce3486cebf856b9f25a43e61c4.tar.gz upstream-7dca1bae82bfd2ce3486cebf856b9f25a43e61c4.tar.bz2 upstream-7dca1bae82bfd2ce3486cebf856b9f25a43e61c4.zip | |
kernel: bump to 4.9.105
Refresh patches.
Drop patches that have been upstreamed:
target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch
target/linux/generic/backport-4.9/095-v4.12-ipv6-Need-to-export-ipv6_push_frag_opts-for-tunnelin.patch
target/linux/generic/pending-4.9/180-net-phy-at803x-add-support-for-AT8032.patch
target/linux/generic/pending-4.9/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch
target/linux/generic/pending-4.9/182-net-qmi_wwan-add-BroadMobi-BM806U-2020-2033.patch
Compile & run tested: ar71xx Archer C7 v2
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Diffstat (limited to 'target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch b/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch deleted file mode 100644 index e785b30eff..0000000000 --- a/target/linux/ar71xx/patches-4.9/106-01-MIPS-ath79-fix-AR724X_PLL_REG_PCIE_CONFIG-offset.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 0f15814bcdf59f10b708a3fba636acb089e9a4f1 Mon Sep 17 00:00:00 2001 -From: Mathias Kresin <dev@kresin.me> -Date: Thu, 30 Mar 2017 15:34:39 +0200 -Subject: [PATCH] MIPS: ath79: fix AR724X_PLL_REG_PCIE_CONFIG offset - -According to the QCA u-boot source the "PCIE Phase Lock Loop -Configuration (PCIE_PLL_CONFIG)" register is for all SoCs except the -QCA955X and QCA956X at offset 0x10. - -Since the PCIE PLL config register is only defined for the AR724x fix -only this value. The value is wrong since the day it was added and isn't -yet used by any driver. - -Signed-off-by: Mathias Kresin <dev@kresin.me> ---- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -167,7 +167,7 @@ - #define AR71XX_AHB_DIV_MASK 0x7 - - #define AR724X_PLL_REG_CPU_CONFIG 0x00 --#define AR724X_PLL_REG_PCIE_CONFIG 0x18 -+#define AR724X_PLL_REG_PCIE_CONFIG 0x10 - - #define AR724X_PLL_FB_SHIFT 0 - #define AR724X_PLL_FB_MASK 0x3ff |