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authorJohn Crispin <john@phrozen.org>2018-08-09 15:59:41 +0200
committerJohn Crispin <john@phrozen.org>2018-08-22 08:09:00 +0200
commit318e19ba6755105bb6cc19937d8fff26cbd2cc6f (patch)
tree2f7c96140932a2770fb767141c7d1e93d29127b0 /target/linux/ar71xx/patches-4.14/632-MIPS-ath79-gpio-enable-set-direction.patch
parente5f56c07d7fab9a6f2201f4100b593349b8ef67d (diff)
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ar71xx: add v4.14 support
adds v4.14 patches for testing but leaves v4.9 as default for now. Signed-off-by: John Crispin <john@phrozen.org>
Diffstat (limited to 'target/linux/ar71xx/patches-4.14/632-MIPS-ath79-gpio-enable-set-direction.patch')
-rw-r--r--target/linux/ar71xx/patches-4.14/632-MIPS-ath79-gpio-enable-set-direction.patch32
1 files changed, 32 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.14/632-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-4.14/632-MIPS-ath79-gpio-enable-set-direction.patch
new file mode 100644
index 0000000000..4cf36325e1
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.14/632-MIPS-ath79-gpio-enable-set-direction.patch
@@ -0,0 +1,32 @@
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
+ void ath79_gpio_output_select(unsigned gpio, u8 val);
++int ath79_gpio_direction_select(unsigned gpio, bool oe);
+ void ath79_gpio_init(void);
+
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -83,3 +83,19 @@ void __init ath79_gpio_output_select(uns
+ /* flush write */
+ (void) __raw_readl(base + reg);
+ }
++
++int ath79_gpio_direction_select(unsigned gpio, bool oe)
++{
++ void __iomem *base = ath79_gpio_base;
++ bool ieq_1 = (soc_is_ar934x() ||
++ soc_is_qca953x());
++
++ if ((ieq_1 && oe) || (!ieq_1 && !oe))
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
++ base + AR71XX_GPIO_REG_OE);
++ else
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
++ base + AR71XX_GPIO_REG_OE);
++
++ return 0;
++}