diff options
author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2019-09-18 12:49:31 +0200 |
---|---|---|
committer | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2019-09-20 13:16:17 +0200 |
commit | fb0c3eb5a31b891d3462311e42f5ec72b78395e8 (patch) | |
tree | b2f40da9a4d394351ad18e8e904ed904d5af2ec2 /target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | |
parent | f3314206545cb42472100bac5424a190170e155f (diff) | |
download | upstream-fb0c3eb5a31b891d3462311e42f5ec72b78395e8.tar.gz upstream-fb0c3eb5a31b891d3462311e42f5ec72b78395e8.tar.bz2 upstream-fb0c3eb5a31b891d3462311e42f5ec72b78395e8.zip |
kernel: bump 4.14 to 4.14.144
Refreshed all patches.
Altered patches:
- 816-pcie-support-layerscape.patch
Fixes:
-CVE-2019-15030
Compile-tested on: cns3xxx, layerscape
Runtime-tested on: cns3xxx
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch')
-rw-r--r-- | target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 4381cb8faf..722d127ec5 100644 --- a/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -307,7 +307,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. return; --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c -@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void) +@@ -62,6 +62,34 @@ static void ar934x_ip2_irq_init(void) irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } @@ -342,7 +342,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) { u32 status; -@@ -143,7 +171,7 @@ void __init arch_init_irq(void) +@@ -149,7 +177,7 @@ void __init arch_init_irq(void) soc_is_ar913x() || soc_is_ar933x()) { irq_wb_chan2 = 3; irq_wb_chan3 = 2; @@ -351,7 +351,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. irq_wb_chan3 = 2; } -@@ -154,6 +182,7 @@ void __init arch_init_irq(void) +@@ -160,6 +188,7 @@ void __init arch_init_irq(void) else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x() || @@ -359,7 +359,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. soc_is_qca955x()) misc_is_ar71xx = false; else -@@ -164,6 +193,8 @@ void __init arch_init_irq(void) +@@ -170,6 +199,8 @@ void __init arch_init_irq(void) if (soc_is_ar934x()) ar934x_ip2_irq_init(); |