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authorGabor Juhos <juhosg@openwrt.org>2008-12-04 16:55:43 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-12-04 16:55:43 +0000
commitab09799f09ea2c72bc8b6e356a8e1b8e48faa9b4 (patch)
tree8ac4891e63aeb16ec5cfb3d41f4b72ca4a144162 /target/linux/ar71xx/files/include
parent4c3e9eeaba289acdde7c276c79a3de5e48056812 (diff)
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[ar71xx] rename reset register definitions
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13516 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/files/include')
-rw-r--r--target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h28
1 files changed, 14 insertions, 14 deletions
diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 5e551a14fd..33614ea354 100644
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -296,20 +296,20 @@ extern void ar71xx_ddr_flush(u32 reg);
/*
* RESET block
*/
-#define RESET_REG_TIMER 0x00
-#define RESET_REG_TIMER_RELOAD 0x04
-#define RESET_REG_WDOG_CTRL 0x08
-#define RESET_REG_WDOG 0x0c
-#define RESET_REG_MISC_INT_STATUS 0x10
-#define RESET_REG_MISC_INT_ENABLE 0x14
-#define RESET_REG_PCI_INT_STATUS 0x18
-#define RESET_REG_PCI_INT_ENABLE 0x1c
-#define RESET_REG_GLOBAL_INT_STATUS 0x20
-#define RESET_REG_RESET_MODULE 0x24
-#define RESET_REG_PERFC_CTRL 0x2c
-#define RESET_REG_PERFC0 0x30
-#define RESET_REG_PERFC1 0x34
-#define RESET_REG_REV_ID 0x90
+#define AR71XX_RESET_REG_TIMER 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
+#define AR71XX_RESET_REG_WDOG_CTRL 0x08
+#define AR71XX_RESET_REG_WDOG 0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
+#define AR71XX_RESET_REG_RESET_MODULE 0x24
+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
+#define AR71XX_RESET_REG_PERFC0 0x30
+#define AR71XX_RESET_REG_PERFC1 0x34
+#define AR71XX_RESET_REG_REV_ID 0x90
#define WDOG_CTRL_LAST_RESET BIT(31)
#define WDOG_CTRL_ACTION_MASK 3